EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 261

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
Configuration Data Decompression
Configuration Data Decompression
© July 2010
Altera Corporation
1
1
Arria II GX devices support configuration data decompression, which saves
configuration memory space and time. This feature allows you to store compressed
configuration data in configuration or other memory devices and transmit this
compressed bitstream to Arria II GX devices. During configuration, the Arria II GX
device decompresses the bitstream in real time and programs its SRAM cells.
Preliminary data indicates that compression typically reduces the configuration
bitstream size by 35 to 55% based on the designs used.
Arria II GX devices support decompression in the FPP (when using a MAX II device
or microprocessor + flash), AS, and PS configuration schemes. The Arria II GX
decompression feature is not available in the JTAG configuration scheme.
When using FPP mode, the intelligent host must provide a DCLK that is ×4 the data
rate. Therefore, the configuration data must be valid for four DCLK cycles.
In PS mode, use the Arria II GX decompression feature, because sending compressed
configuration data reduces configuration time.
When you enable compression, the Quartus II software generates configuration files
with compressed configuration data. This compressed file reduces the storage
requirements in the configuration device or flash memory, and decreases the time
needed to transmit the bitstream to the Arria II GX device. The time required by a
Arria II GX device to decompress a configuration file is less than the time needed to
transmit the configuration data to the device.
There are two ways to enable compression for Arria II GX bitstreams: before design
compilation (in the Compiler Settings menu) and after design compilation (in the
Convert Programming Files window).
To enable compression in the project’s Compiler Settings menu, perform the following
steps:
1. On the Assignments menu, click Device to bring up the Settings dialog box.
2. After selecting your Arria II GX device, open the Device and Pin Options dialog
3. In the Configuration settings tab, enable the check box for Generate compressed
box.
bitstreams (as shown in
Figure
9–19).
Arria II GX Device Handbook, Volume 1
9–41