EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 169
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
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- EP2AGX95EF29I5N PDF datasheet #6
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Chapter 7: External Memory Interfaces in Arria II GX Devices
Arria II GX Memory Interfaces Pin Support
Figure 7–9. Number of DQ/DQS Groups per Bank in EP2AGX190 and EP2AGX260 Devices in the 1152-Pin FineLine BGA
Package (1),
Notes to
(1) All I/O pin counts include 12 dedicated clock inputs (CLK4 to CLK15) that you can use for data inputs.
(2) Several configuration pins in Bank 6A are shared with DQ/DQS pins. You cannot use a 4 DQ/DQS group with any of its pin members used for
© July 2010 Altera Corporation
configuration purposes. Ensure that the DQ/DQS groups you have chosen are not also used for configuration.
Figure
7–9:
(2)
I/O Bank 3B
32 User I/Os
×16/×18=1
×32/×36=0
32 User I/Os
I/O Bank 8B
×16/×18=1
×32/×36=0
×8/×9=2
×8/×9=2
×4=4
×4=4
Figure 7–9
EP2AGX190 and EP2AGX260 devices in the 1152-pin FineLine BGA package.
The DQS and DQSn pins are listed in the Arria II GX pin tables as DQSXY and DQSnXY,
respectively, where X denotes the DQ/DQS grouping number and Y denotes whether
the group is located on the top (T), bottom (B), or right (R) side of the device. The
DQ/DQS pin numbering is based on ×4 mode.
shows the number of DQ/DQS groups per bank in Arria II GX
70 User I/Os
I/O Bank 3A
×16/×18=2
×32/×36=1
74 User I/Os
×8/×9=4
I/O Bank 8A
×16/×18=2
×32/×36=1
EP2AGX190 and EP2AGX260 Devices
×4=8
×8/×9=4
×4=8
in the 1152-Pin FineLine BGA
70 User I/Os
I/O Bank 7A
74 User I/Os
I/O Bank 4A
×16/×18=2
×32/×36=1
×16/×18=2
×32/×36=1
×8/×9=4
×8/×9=4
×4=8
×4=8
I/O Bank 4B
32 User I/Os
×16/×18=1
×32/×36=0
32 User I/Os
I/O Bank 7B
×8/×9=2
×16/×18=1
×32/×36=0
×8/×9=2
×4=4
×4=4
Arria II GX Device Handbook, Volume 1
66 User I/Os
I/O Bank 6B
I/O Bank 5A
32 User I/Os
I/O Bank 5B
66 User I/Os
I/O Bank 6A
32 User I/Os
×16/×18=1
×32/×36=0
×16/×18=1
×32/×36=0
×16/×18=2
×32/×36=1
×16/×18=2
×32/×36=1
×8/×9=2
×8/×9=2
×8/×9=4
×8/×9=4
×4=4
×4=4
×4=8
×4=8
7–11
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