EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 147
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 6: I/O Features in Arria II GX Devices
Arria II GX OCT Support
LVDS Input On-Chip Differential Termination
© July 2010 Altera Corporation
Table 6–6
Table 6–6. Selectable I/O Standards with On-Chip Series Termination with and without Calibration
All I/O banks in Arria II GX devices support input R
value of 100 , as shown in
support R
Figure 6–5. Differential Input On-Chip Termination
3.0-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-15 Class I
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
HSTL-15 Class II
HSTL-12 Class I
HSTL-12 Class II
lists the I/O standards that support R
I/O Standard
D
OCT. You can enable R
Transmitter
Figure
D
6–5. However, not all input differential pins
OCT when both the V
Right I/O ()
Z
Z
O
O
= 50 Ω
= 50 Ω
50
25
50
25
50
25
50
25
50
25
50
25
50
25
50
50
25
50
25
50
25
R
S
OCT Termination Setting
S
OCT with and without calibration.
D
OCT with a nominal resistance
Arria II GX Device Handbook, Volume 1
CCIO
100 Ω
Top and Bottom I/O ()
and V
Receiver
CCPD
50
25
50
25
50
25
50
25
50
25
50
25
50
25
50
50
25
50
25
50
25
is set to 2.5 V.
6–13
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