EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 227
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
Configuration Schemes
Table 9–2. Arria II GX Configuration Schemes
Raw Binary File Size
© July 2010
FPP
FPP with design security feature,
decompression, or both enabled
PS
AS with or without remote system upgrade
JTAG-based configuration
Notes to
(1) Configuration voltage standard applied to the V
(2) These modes are only supported when using a MAX II device or a microprocessor with flash memory for configuration. In these modes, the
(3) JTAG-based configuration takes precedence over other configuration schemes, which means MSEL pin settings are ignored. JTAG-based
(4) Do not leave MSEL pins floating. Connect them to V
host system must output a DCLK that is ×4 the data rate.
configuration does not support the design security or decompression features.
If you only use the JTAG configuration, Altera recommends that you connect the MSEL pins to GND.
Table
Configuration Scheme
Altera Corporation
9–2:
1
To avoid problems with detecting an incorrect configuration scheme, hardwire the
MSEL[] pins to V
the MSEL[] pins by a microprocessor or another device.
Table 9–3
Table 9–3. Arria II GX Uncompressed .rbf Sizes
EP2AGX45
EP2AGX65
EP2AGX95
EP2AGX125
EP2AGX190
EP2AGX260
(3)
(2)
lists the uncompressed .rbf configuration file sizes for Arria II GX devices.
Device
CCIO
CC PD
MSEL3
power supply in which the configuration pins reside.
CCPD
or GND without pull-up or pull-down resistors. Do not drive
(4)
0
0
0
1
0
1
1
1
0
1
1
1
or GND. These pins support the non-JTAG configuration scheme used in production.
MSEL2
(4)
0
1
0
0
0
0
0
0
0
1
1
1
MSEL1
(4)
0
1
0
0
1
0
1
1
1
0
1
1
Data Size (bits)
MSEL0
29,599,704
29,599,704
50,376,968
50,376,968
82,763,208
82,763,208
(4)
0
1
1
0
0
1
0
1
1
1
0
1
Arria II GX Device Handbook, Volume 1
POR Delay
Standard
Standard
Standard
Standard
Fast
Fast
Fast
Fast
Fast
Fast
Fast
Fast
—
Standard (V)
Configuration
3.3, 3.0, 2.5
3.3, 3.0, 2.5
3.3, 3.0, 2.5
3.3, 3.0, 2.5
Voltage
3.0, 2.5
3.0, 2.5
1.8
1.8
1.8
1.8
3.3
3.3
—
(1)
9–7
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