EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 146
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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6–12
Arria II GX Device Handbook, Volume 1
Figure 6–3. Arria II GX On-Chip Series Termination without Calibration
To use OCT for:
■
■
On-Chip Series Termination with Calibration
Arria II GX devices support R
calibration circuit compares the total impedance of the I/O buffer to the external
25- ±1% or 50- ±1% resistors connected to the RUP and RDN pins, and dynamically
enables or disables the transistors until they match.
The R
occurs at the end of device configuration. When the calibration circuit finds the
correct impedance, it powers down and stops changing the characteristics of the
drivers.
Figure 6–4. Arria II GX On-Chip Series Termination with Calibration
SSTL Class I standard—select the 50-on-chip series termination setting, thus
eliminating the external 25- R
SSTL Class II standard—select the 25- on-chip series termination setting (to
match the 50- transmission line and the near-end external 50- pull-up to V
S
shown in
Figure 6–4
Series Termination
Series Termination
Arria II GX Driver
Arria II GX Driver
V
V
GND
GND
CCIO
CCIO
is the intrinsic impedance of transistors. Calibration
S
R
R
R
R
OCT with calibration in all banks. The R
S
S
S
S
S
(to match the 50- transmission line).
Z
Z
O
O
= 50
= 50
Chapter 6: I/O Features in Arria II GX Devices
Receiving
Receiving
Device
Device
© July 2010 Altera Corporation
Arria II GX OCT Support
S
OCT
TT
).
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