EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 184
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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7–26
Revision History
Table 7–6. Document Revision History
Arria II GX Device Handbook, Volume 1
July 2010
November 2009
June 2009
February 2009
February 2009
Date
Version
Table 7–6
3.0
2.0
1.2
1.1
1.0
shows the revision history for this chapter.
Updated for Arria II GX v10.0 release:
■
■
■
Updated for Arria II GX v9.1 release:
■
■
■
■
■
■
■
■
■
Updated Table 7–1 and Table 7–2.
Initial release.
Updated
the
Handbook and removing “Table 7–1: Memory Interface Pin Utilization”.
Update DLL numbering to match with the Quartus II software.
Minor text edits.
Updated Table 7–1, Table 7–2, and Table 7–5.
Updated Figure 7–1, Figure 7–2, Figure 7–3, Figure 7–11, Figure 7–12, Figure 7–13,
Figure 7–15, and Figure 7–16.
Updated the “Arria II GX External Memory Interface Features” section.
Added new “Combining ×16/×18 DQ/DQS Groups for ×36 QDR II+/QDR II SRAM
Interface” section.
Minor text edits.
Added Table 7–2.
Updated Table 7–1, Table 7–3, and Table 7–5.
Updated Figure 7–1, Figure 7–3, Figure 7–4, Figure 7–5, Figure 7–6, Figure 7–7,
Figure 7–8, Figure 7–9, and Figure 7–11.
Updated “Introduction” and “DLL” sections.
Section I. Device and Pin Planning
“Arria II GX Memory Interfaces Pin Support”
Chapter 7: External Memory Interfaces in Arria II GX Devices
Changes Made
in volume 2 of the External Memory Interface
section by adding reference to
© July 2010 Altera Corporation
Revision History
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