EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 199
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices
Differential Receiver
Figure 8–12. Receiver Datapath in DPA Mode
Notes to
(1) All disabled blocks and signals are grayed out.
(2) In SDR and DDR modes, the data width from the IOE is 1 and 2, respectively.
(3) The rx_out port has a maximum data width of 10.
© July 2010
rx_divfwdclk
rx_outclock
Fabric
FPGA
rx_out
Figure
Altera Corporation
8–12:
10
DPA Mode
In DPA mode, the DPA circuitry automatically chooses the optimal phase between the
source-synchronous reference clock and the input serial data to compensate for the
skew between the two signals. The reference clock must be a differential signal.
Figure 8–12
DPA_diffioclk clock to write serial data into the synchronizer. Use the
LVDS_diffioclk clock to read the serial data from the synchronizer. Use the same
LVDS_diffioclk clock in the data realignment and deserializer blocks.
IOE Supports SDR, DDR, or Non-Registered Datapath
(LOAD_EN, diffioclk)
2
Deserializer
DOUT DIN
shows the DPA mode receiver datapath block diagram. Use the
IOE
Center/Corner PLL
2
(Note
3
DOUT DIN
Multiplier
Bit Slip
Clock
(LVDS_LOAD_EN,
LVDS_diffioclk,
1), (2),
rx_outclk)
diffioclk
(3)
rx_inclock
DOUT DIN
Synchronizer
8 Serial LVDS
Clock Phases
LVDS Receiver
3
Arria II GX Device Handbook, Volume 1
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
Retimed
Data
DPA Clock
DPA Circuitry
DIN
+
LVDS Clock Domain
DPA Clock Domain
rx_in
8–15
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