EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 117
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 5: Clock Networks and PLLs in Arria II GX Devices
PLLs in Arria II GX Devices
Clock Switchover
Figure 5–19. Automatic Clock Switchover Circuit Block Diagram
© July 2010
Altera Corporation
inclk0
inclk1
The clock switchover feature allows the PLL to switch between two reference input
clocks. Use this feature for clock redundancy or for a dual-clock domain application
such as in a system that turns on the redundant clock if the previous clock stops
running. Your design can perform clock switchover automatically, when the clock is
no longer toggling or based on a user control signal (clkswitch).
The following clock switchover modes are supported in Arria II GX PLLs:
■
■
■
Arria II GX PLLs support a fully configurable clock switchover capability.
shows the block diagram of the switchover circuit built into the PLL. When the
current reference clock is not present, the clock sense block automatically switches to
the backup clock for PLL reference. The clock switchover circuit also sends out three
status signals—clkbad[0], clkbad[1], and activeclock—from the PLL to
implement a custom switchover circuit in the logic array. You can select a clock source
as the backup clock by connecting it to the inclk1 port of the PLL in your design.
Automatic switchover—The clock sense circuit monitors the current reference
clock and if it stops toggling, automatically switches to the other clock (inclk0 or
inclk1).
Manual clock switchover—Clock switchover is controlled with the clkswitch
signal in this mode. When the clkswitch signal goes from logic low to logic
high, and stays high for at least three clock cycles, the reference clock to the PLL is
switched from inclk0 to inclk1, or vice-versa.
Automatic switchover with manual override—This mode combines modes 1 and
2. When the clkswitch signal goes high, it overrides automatic clock switchover
mode.
muxout
clksw
n Counter
Sense
Clock
refclk
Switchover
Machine
State
Clock Switch
Control Logic
PFD
Arria II GX Device Handbook, Volume 1
fbclk
clkbad0
clkbad1
activeclock
clkswitch
Figure 5–19
5–25
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