EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 185
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
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- EP2AGX95EF29I5N PDF datasheet #6
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© July 2010
AIIGX51008-3.0
Altera Corporation
This chapter describes the high-speed differential I/O features and resources as well
as the functionality of the serializer/deserializer (SERDES) and dynamic phase
alignment (DPA) circuitry in Arria
in Arria II GX devices allows for high-speed LVDS interface on the top, bottom, and
right sides of the device. The left side of the device is occupied by high-speed
transceiver blocks. Dedicated SERDES and DPA circuitry are implemented on the
right side of the device to further enhance LVDS interface performance in the device.
This chapter contains the following sections:
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Arria II GX devices have the following dedicated circuitry for high-speed differential
I/O support:
■
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Arria II GX devices support the following differential I/O standards:
■
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“LVDS Channels” on page 8–2
“LVDS SERDES and DPA Block Diagram” on page 8–5
“Differential Transmitter” on page 8–7
“Differential Receiver” on page 8–9
“Programmable Pre-Emphasis and Programmable V
“Differential I/O Termination” on page 8–18
“PLLs” on page 8–18
“LVDS and DPA Clock Networks” on page 8–19
“Source-Synchronous Timing Budget” on page 8–20
“Differential Pin Placement Guidelines” on page 8–23
“Setting Up an LVDS Transmitter or Receiver Channel” on page 8–33
Differential I/O buffer
Transmitter serializer
Receiver deserializer
Data realignment
DPA
Synchronizer (FIFO buffer)
Phase-locked loops (PLLs)
LVDS
mini-LVDS
Reduced swing differential signaling (RSDS)
Low-voltage positive emitter-coupled logic (LVPECL)
Bus LVDS (BLVDS)
8. High-Speed Differential I/O Interfaces
®
II GX devices. The new modular I/O architecture
and DPA in Arria II GX Devices
OD
Arria II GX Device Handbook, Volume 1
.” on page 8–17
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