EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 19
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
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Chapter 1: Arria II GX Device Family Overview
Arria II GX Device Architecture
High-Speed Transceiver Features
© July 2010 Altera Corporation
Arria II GX devices integrate up to 16 transceivers on a single device. The transceiver
block is optimized for cost and power consumption. Arria II GX transceivers support
the following features:
■
■
■
■
Configurable pre-emphasis and equalization, and adjustable output differential
voltage
Flexible and easy-to-configure transceiver datapath to implement proprietary
protocols
Signal integrity features
■
■
■
■
Diagnostic features
■
■
■
■
■
Programmable transmitter pre-emphasis to compensate for inter-symbol
interference (ISI)
User-controlled five-stage receiver equalization with up to 7 dB of
high-frequency gain
On-die power supply regulators for transmitter and receiver PLL charge pump
and voltage-controlled oscillator (VCO) for superior noise immunity
Calibration circuitry for transmitter and receiver on-chip termination (OCT)
resistors
Serial loopback from the transmitter serializer to the receiver CDR for
transceiver physical coding sublayer (PCS) and physical media attachment
(PMA) diagnostics
Parallel loopback from the transmitter PCS to the receiver PCS with built-in self
test (BIST) pattern generator and verifier
Reverse serial loopback pre- and post-CDR to transmitter buffer for physical
link diagnostics
Loopback master and slave capability in PCIe hard IP blocks
Support for protocol features such as MSB-to-LSB transmission in a
SONET/SDH configuration and spread-spectrum clocking in a PCIe
configuration
Arria II GX Device Handbook, Volume 1
1–5
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