EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 15
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Highlights
© July 2010 Altera Corporation
AIIGX51001-3.0
The Arria
cost-optimized, 40-nm device family architecture features a low-power,
programmable logic engine and streamlined transceivers and I/Os. Common
interfaces, such as the Physical Interface for PCI Express
and DDR3 memory are easily implemented in your design with the Quartus
software, the SOPC Builder design software, and a broad library of hard and soft
intellectual property (IP) solutions from Altera
designing for applications requiring transceivers operating at up to 6.375 Gbps fast
and easy.
This chapter contains the following sections:
■
■
■
The Arria II GX device features consist of the following highlights:
■
■
■
■
“Highlights”
“Arria II GX Device Architecture” on page 1–4
“Reference and Ordering Information” on page 1–11
40-nm, low-power FPGA engine
■
■
■
High-performance digital signal processing (DSP) blocks up to 380 MHz
■
■
■
Maximum system bandwidth
■
■
Complete PIPE protocol solution with an embedded hard IP block that provides
physical interface and media access control (PHY/MAC) layer, Data Link layer,
and Transaction layer functionality
Adaptive logic module (ALM) offers the highest logic efficiency in the industry
Eight-input fracturable look-up table (LUT)
Memory logic array blocks (MLABs) for efficient implementation of small
FIFOs
Configurable as 9 × 9-bit, 12 × 12-bit, 18 × 18-bit, and 36 × 36-bit full-precision
multipliers as well as 18 × 36-bit high-precision multiplier
Hardcoded adders, subtractors, accumulators, and summation functions
Fully-integrated design flow with the MATLAB and DSP Builder software
from Altera
Up to 16 full-duplex clock data recovery (CDR)-based transceivers supporting
rates between 155 Mbps and 6.375 Gbps
Dedicated circuitry to support physical layer functionality for popular serial
protocols, including PCIe Gen1, Gbps Ethernet, Serial RapidIO
Common Public Radio Interface (CPRI), OBSAI, SD/HD/3G/ASI Serial
Digital Interface (SDI), XAUI, HiGig/HiGig+, SATA/Serial Attached SCSI
(SAS), GPON, SerialLite II, Fiber Channel, and SONET/SDH
®
II GX device family is designed specifically for ease-of-use. The
1. Arria II GX Device Family Overview
®
. The Arria II GX device family makes
®
(PIPE) (PCIe
Arria II GX Device Handbook, Volume 1
®
®
(SRIO),
), Ethernet,
®
II
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