EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 140

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

6–6
Figure 6–2. Arria II GX IOE Structure
3.3-V I/O Interface
Arria II GX Device Handbook, Volume 1
Write
To
Core
To
Core
Data
form
Core
Read
Data
to
Core
CQn
OE
from
Core
DQS
clkin
f
Figure 6–2
For more information about I/O registers and how they are used for memory
applications, refer to the
Arria II GX I/O buffers are fully compatible with 3.3-V I/O standards. You can use
them as transmitters or receivers in your system. The output high voltage (V
output low voltage (V
meet the 3.3-V I/O standard specifications defined by EIA/JEDEC Standard JESD8-B
with margin when the Arria II GX V
To ensure device reliability and proper operation when interfacing with a 3.3-V I/O
system with Arria II GX devices, it is important to ensure that the absolute maximum
ratings are not violated. Altera recommends performing IBIS simulation to determine
that the overshoot and undershoot voltages are in the guidelines. There are several
techniques that you can use to limit overshoot and undershoot voltages, though none
are required.
to internal Cells
Input Pin Delay
Synchronization
Registers
Input Register Delay
shows the Arria II GX IOE structure.
DQS Bus
to
Output Register
Output Register
OE Register
OE Register
D
D
D
D
PRN
PRN
PRN
PRN
Q
Q
Q
Q
OL
), input high voltage (V
External Memory Interfaces in Arria II GX Devices
to Input Register
Input Pin Delay
Input Register
Input Register
D
D
PRN
PRN
Q
Q
CCIO
Output Pin
Delay
Output Enable
Input Register
voltage is powered by 3.3 V or 3.0 V.
Programmable
D
Pin Delay
Strength and
Slew Rate
PRN
Current
Control
Q
Open Drain
IH
), and input low voltage (V
Output Buffer
Chapter 6: I/O Features in Arria II GX Devices
Input Buffer
V
CCIO
© July 2010 Altera Corporation
V
CCIO
Pull-Up Resistor
Programmable
Termination
Calobration
From OCT
On-Chip
Arria II GX I/O Structure
Bus-Hold
Block
Circuit
chapter.
IL
OH
) levels
),