EP3C25F324I7 Altera, EP3C25F324I7 Datasheet - Page 53

• Manufacturer Part Number: EP3C25F324I7
• Description: IC CYCLONE III FPGA 25K 324 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25F324I7

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 215
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 215
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Chapter 3: Memory Blocks in the Cyclone III Device Family
Design Considerations
© December 2009
Altera Corporation
Same-Port Read-During-Write Mode
This mode applies to a single-port RAM or the same port of a true dual-port RAM. In
the same port read-during-write mode, there are two output choices: New Data mode
(or flow-through) and Old Data mode. In New Data mode, new data is available on
the rising edge of the same clock cycle on which it was written. In Old Data mode, the
RAM outputs reflect the old data at that address before the write operation proceeds.
When using New Data mode together with byteena, you can control the output of
the RAM. When byteena is high, the data written into the memory passes to the
output (flow-through). When byteena is low, the masked-off data is not written into
the memory and the old data in the memory appears on the outputs. Therefore, the
output can be a combination of new and old data determined by byteena.
Figure 3–15
read-during-write behavior with both New Data and Old Data modes, respectively.
Figure 3–15. Same Port Read-During Write: New Data Mode
Figure 3–16. Same Port Read-During-Write: Old Data Mode
q_a (asynch)
q_a (asynch)
address_a
address_a
wren_a
wren_a
data_a
rden_a
rden_a
data_a
clk_a
clk_a
and
Figure 3–16
A
A
a0(old data)
show sample functional waveforms of same port
A
a0
a0
B
B
A
B
C
C
B
C
D
D
a1(old data)
D
Cyclone III Device Handbook, Volume 1
a1
a1
E
E
D
E
F
F
E
F
3–17