EP3C25F324I7 Altera, EP3C25F324I7 Datasheet - Page 246

• Manufacturer Part Number: EP3C25F324I7
• Description: IC CYCLONE III FPGA 25K 324 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25F324I7

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 215
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 215
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

9–86
Cyclone III Device Handbook, Volume 1
1
Table 9–29. Remote System Upgrade Previous State Register 1 and Previous State Register 2
Contents in Status Register
If a capture is inappropriately done, for example, capturing a previous state before the
system has entered remote update application configuration for the first time, a value
will output from the shift register to indicate that the capture was incorrectly called.
Remote System Upgrade State Machine
The remote system upgrade control and update registers have identical bit
definitions, but serve different roles
can only be updated when the device is loaded with a factory configuration image,
the update register writes are controlled by the user logic, and the control register
writes are controlled by the remote system upgrade state machine.
In factory configurations, the user logic should send the option bits (Cd_early and
Osc_int), the configuration address, and watchdog timer settings for the next
application configuration bit to the update register. When the logic array
configuration reset (RU_nCONFIG) goes high, the remote system upgrade state
machine updates the control register with the contents of the update register and
starts system reconfiguration from the new application page.
To ensure the successful reconfiguration between the pages, assert RU_nCONFIG
signal for a minimum of 250 ns. This is equivalent to strobing the reconfig input of
the ALTREMOTE_UPDATE megafunction high for a minimum of 250 ns.
If there is an error or reconfiguration trigger condition, the remote system upgrade
state machine directs the system to load a factory or application configuration (based
on mode and error condition) by setting the control register accordingly.
Note to
(1) The MSEL pin settings are in the AS configuration scheme.
Status Register Bit
25:24
Table
23:0
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
30
29
28
27
26
9–29:
nCONFIG source
CRC error source
nSTATUS source
User watchdog timer source
Remote system upgrade
nCONFIG source
Master state machine current state
Boot address
(Note 1)
Definition
(Table 9–26 on page
One-hot, active-high field that
describes the reconfiguration source
that caused the Cyclone III device
family to leave the previous application
configuration. If there is a tie, the
higher bit order indicates precedence.
For example, if nCONFIG and remote
system upgrade nCONFIG reach the
reconfiguration state machine at the
same time, the nCONFIG precedes
the remote system upgrade
nCONFIG.
The state of the master state machine
during reconfiguration causes the
Cyclone III device family to leave the
previous application configuration.
The address used by the configuration
scheme to load the previous
application configuration.
9–83). While both registers
© December 2009 Altera Corporation
Description
Remote System Upgrade