EP3C25F324I7 Altera, EP3C25F324I7 Datasheet - Page 264

• Manufacturer Part Number: EP3C25F324I7
• Description: IC CYCLONE III FPGA 25K 324 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25F324I7

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 215
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 215
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

11–10
Table 11–8. CRC Block Input and Output Ports (Part 2 of 2)
Recovering from CRC Errors
Cyclone III Device Handbook, Volume 1
.ldsrc (<ldsrc
source>)
.crcerror
(<crcerror
indicator
output>)
.regout
(<registered
output>)
.cyclecomplete
(<cyclone
complete
indicator
output>)
Port
The system that the Altera FPGA resides in must control device reconfiguration. After
detecting an error on the CRC_ERROR pin, strobing the nCONFIG low directs the
system to perform the reconfiguration at a time when it is safe for the system to
reconfigure the FPGA.
When the data bit is rewritten with the correct value by reconfiguring the device, the
device functions correctly.
While soft errors are uncommon in Altera devices, certain high-reliability applications
might require a design to account for these errors.
Input/Output
Output
Output
Output
Input
This signal is an input into the error detection block. If ldsrc=0, the
pre-computed CRC register is selected for loading into the 32-bit shift register
at the rising edge of clk when shiftnld=0. If ldsrc=1, the signature
register (result of the CRC calculation) is selected for loading into the shift
register at the rising edge of clk when shiftnld=0. This port is ignored
when shiftnld=1. This port is required.
This signal is the output of the cell that is synchronized to the internal
oscillator of the device (80-MHz internal oscillator) and not to the clk port. It
asserts high if the error block detects that a SRAM bit has flipped and the
internal CRC computation has shown a difference with respect to the pre-
computed value. This signal must be connected either to an output pin or a
bidirectional pin. If it is connected to an output pin, you can only monitor the
CRC_ERROR pin (the core cannot access this output). If the CRC_ERROR
signal is used by core logic to read error detection logic, this signal must be
connected to a BIDIR pin. The signal is fed to the core indirectly by feeding a
BIDIR pin that has its output enable port connected to VCC
page
This signal is the output of the error detection shift register synchronized to
the clk port, to be read by core logic. It shifts one bit at each cycle, so you
should clock the clk signal 31 cycles to read out the 32 bits of the shift
register.
This signal is for cycloneiiils_crcblock only. This output signal is
synchronized to the internal oscillator of the device (80-MHz internal
oscillator), and not to the clk port. The signal asserts high for one clock
cyclone every time an error detection cyclone completes.
11–8).
Chapter 11: SEU Mitigation in the Cyclone III Device Family
Definition
© December 2009 Altera Corporation
Recovering from CRC Errors
(Figure 11–3 on