S19252PBIDB Applied Micro Circuits Corporation, S19252PBIDB Datasheet - Page 53

• Manufacturer Part Number: S19252PBIDB
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S19252PBIDB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 23: Output Pin Assignments and Descriptions (Continued)
Table 24: S19252 JTAG Pin Assignments and Descriptions
Revision 5.03
RX_BIST_ERR
TX_RX_ALARM
BIST_ACTIVE
BER_COUNT[11:0]
BER_OVERFLOW
TERM_COUNT
TCK
TDI
TMS
TDO
TRSTB
Pin Name
Pin Name
Pull down
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Register
& Regis-
Register
Register
0x84-85h
Register
Register
Pull up
Pull up
Pull up
Pull Up
0X89H
Level
0X85h
CMOS
0x85h
0x83h
Level
LV
ter
AppliedMicro - Confidential and Proprietary
I/O
O
O
O
O
O
O
I/O
O
I
I
I
I
Pin#
L15
Pin#
M12
M11
L10
L12
L11
Common Outputs
Receive Built-In Self Test Error. This output indicates a bit error in
the receive built-in self test loop.
Transmit and Receive Alarm Output. This output is an electrical
“OR” of all the transmit and receive alarms [[(“NOT” TX_LOCKDET)
“OR” (PHERR)] “OR” (“NOT” RX_LOCKDET)].
Built In Self Test Active (BIST_ACTIVE). This output indicates that
the BIST checker is active and is progressively checking data. This
output can be accessed through the serial bus register.
Bit Error Rate Count (BER_COUNT[11:0]). This output holds the bit
error rate being received by the checker with the exponent being
determined by the BER_SELECT[2:0] input. This output can be
accessed through the serial bus register. Read BER_COUNT[3:0]
first then BER_COUNT[11:4] for accurate error count information.
Bit Error Rate Overflow (BER_OVERFLOW). Active high. This out-
put indicates that the BER_COUNT[11:0] has overflowed and bit error
rate range select (BER_SELECT[2:0]) needs to be changed. This sig-
nal is latched high. This output can be accessed through the serial
bus register.
Terminal Count Monitor (TERM_COUNT). This output monitors for
the terminal count of the PRBS checker. The terminal count is set by
the BER_SELECT[2:0] register. See Table 14 for details. This output
can be accessed through the serial bus register.
Test clock. JTAG input clock used to sample data on the TDI and
TDO pins
Test data in. Input pin for serial data stream to be sent to the
S19252. TDI is sampled on the rising edge of TCK.
Test mode select. Controls the operating mode of the JTAG inter-
face. TMS is sampled on the rising edge of TCK.
Test data out. Output pin for serial data stream from the S19252.
TDO is updated on the falling edge of TCK.
Test port reset. Active-low input used to reset the JTAG interface.
Description
Description
S19252 Data Sheet
53