s19252 Applied Micro Circuits Corporation (AMCC), s19252 Datasheet

s19252

Manufacturer Part Number

s19252

Description

Sts-192 Sonet/sdh/fec/gbe/fc 16-bit Edc Transceiver With 10 G Clock

Manufacturer

Applied Micro Circuits Corporation (AMCC)

Datasheet

1.S19252.pdf (2 pages)

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S19252

STS-192 SONET/SDH/FEC/GbE/FC 16-bit EDC Transceiver with 10 G Clock

Features

• Operational from 9.9 Gbps to 11.3 Gbps

• Built-In Self Test (BIST) with Error Counter

• On-chip High-Frequency PLLs for Clock Recov-

• 16-bit LVDS Parallel Data Path

• TX and RX Lock Detect Indicators

• Reference Loop Timing Modes

• Line and Diagnostic Loopback Mode for Faulty

• -40°C to 85°C Industrial Temperature Range

• Supports MDIO, I2C and SPI serial interface

• Complies with applicable OIF SFI-4 Phase 1,

• 2000 V ESD rating on low speed pins, 1000 V

• 15 mm x 15 mm

• 1.2 W typical

• JTAG support

Transmitter Features

• Ref. Freq. of 155.52 or 622.08 MHz (or eq. FEC

• Internal, Self-Initializing FIFO to Decouple

• Programmable TSD Output Differential Swing

• 10 G Transmitter Serial Clock Output

• Duo Binary Encoding

Receiver Features

• LOS/RSSI

• ISI compensation. Tolerates additional 350 ps/

• Tolerates up to 36” of Standard FR-4 Material

• Adaptive Post-Amplifier Offset Adjust

• Phase Adjust of -0.11 to +0.085 UI

• Ref. Freq. of 155.52 MHz or 622.08 MHz (or eq.

• Capability to Interface with Single-Ended or

• Input Sensitivity of 10 mV p-p (one wire or

Applications

• SONET/SDH and 10GbE-Based Transmission

• Section Repeaters

• Add Drop Multiplexers (ADM)

• Broad-Band Cross-Connects

• Fiber Optic Test Equipment

ery and Clock Gen.

Node Identification

Telcordia/ITU-T, 300-pin MSA, IEEE 802.3ae

and XFP MSA Standards

on high speed I/Os

Green / RoHS compliant lead free option.

rate); Common 10 GbE/10 G FC Ref. of

156.25 MHz or 159.375 MHz for 10 G FC;

Divide by 16 or 64 of the TX rates

Transmit Clocks

nm of chromatic dispersion with an OSNR

penalty of 1.0dB over a traditional demux

FEC rate); Common ref. of 156.25 MHz for 10

GbE/10 GFC or 159.375 MHz for 10 GFC; Divide

by 16 or 64 of the RX rates

Differential TIAs (Center Tap Option)

two wire) at 10

Systems & Modules

-12

, 0.8 mm pitch package with

BER

Description

The S19252 MUX/DeMux chip is a fully

integrated serialization/de-serialization SONET

STS-192/10 GB Ethernet/Fiber Channel

transceiver with Electronic Dispersion

Compensation (EDC). This device can be used

to compensate channel impairments caused by

Single Mode Fiber (SMF) and copper medium.

The chip performs all necessary parallel-to-serial

and serial-to-parallel functions in conformance

with SONET/SDH, 10 Gigabit Ethernet (10 GbE)

and 10 Gigabit Fibre Channel (10 G FC)

transmission standards. The figure below shows

a typical network application. The other

application block diagrams are shown on

page 2.

On-chip clock synthesis PLL components are

contained in the S19252 chip, allowing the use

of a slower external transmit clock reference.

The chip can be used with 155.52 MHz or 622.08

MHz (or equivalent FEC/10 GbE/10 G FC rates)

reference clocks, in support of existing system

clocking schemes. The low-jitter LVDS interface

guarantees compliance with the bit-error rate

requirements of the Telcordia and ITU-T

standards.

Overview

The S19252 transceiver incorporates SONET/

SDH/10 GbE/10 G Fibre Channel serialization

and deserialization functions. This chip can be

used to implement the front end of SONET/10

GbE/10 G Fibre Channel equipment, which

consists primarily of the serial transmit interface

and the serial receive interface. The chip

includes parallel-to-serial, and serial-to-parallel

conversion and system timing.

KHATANGA

RUBICON

HUDSON

MEKONG

GANGES

AMCC

S19252

AMCC

System Block Diagram with the S19252

10G clk

data

TIA

OTX

ORX

AMCC Suggested Interface Devices

The sequence of operations is as follows:

Transmitter Operations

Receiver Operations

Internal clocking and control functions are

transparent to the user.

GANGES (S19202)

Rubicon/Niagara

HUDSON (S19203)

MEKONG (S19204)

KHATANGA (S19205)

S19233

• 16-bit parallel input

• Parallel-to-serial conversion

• Serial data output

• Serial clock output

• Serial input to post-Amplifier

• ISI compensation

• LOS and RSSI

• Threshold and phase adjustment for improved BER

• Clock and data recovery

• Serial-to-parallel conversion

• 16-bit parallel data and clock output

ORX

OTX

PRODUC T BRIEF

TIA

10G Clk

data

STS-192 POS/ATM SONET/SDH

Mapper

OC-192/48/12/3 DW/FEC/PM and

ASYNC Mapper Device

Variable Rate Digital Wrapper

Framer/Deframer, Performance

Monitor, and FEC Device

STS-192 Pointer Processor

STS-192c SONET/SDH Framer/Map-

per with Integrated MAC

Dual CDR imbedded in XFP module

S19252

AMCC

KHATANGA

MEKONG

RUBICON

GANGES

HUDSON

AMCC

Related parts for s19252

s19252 Summary of contents

Page 1

... Transmitter Features On-chip clock synthesis PLL components are • Ref. Freq. of 155.52 or 622.08 MHz (or eq. FEC contained in the S19252 chip, allowing the use rate); Common 10 GbE/ Ref slower external transmit clock reference. 156.25 MHz or 159.375 MHz for 10 G FC; ...

Page 2

... Figure 1. Mid-Plane Application Block Diagram Enable Adaptive Post-Amplifier Offset Control Enable Adaptive ISI Mitigation Disable EDC / 10G Clock MDIO/I2C /SPI ASIC 16 OR AMCC XFP MODULE FRAMER S19252 OR 16 FEC Compensates up to 24" of FR-4 Figure 2. XFP Application Block Diagram C 16 300 MSA MODULE Laser O Laser ...

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