S19252PBIDB Applied Micro Circuits Corporation, S19252PBIDB Datasheet - Page 32

• Manufacturer Part Number: S19252PBIDB
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S19252PBIDB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

S19252 Data Sheet
MDIO Bus and Address Register
S19252 uses (as Default) a simple bi-directional two-
wire bus for efficient inter-IC control. This bus reads
from and writes into most of the S19252 control logic.
The following are some important features of MDIO
bus:
•
•
The register mapping has been outlined below. The
serial port interface is based on the IEEE802.3u MII
Management
occurs across two wires and is formatted in frames.
The two wires are clock (MDC) and data (MDIO). There
is no preamble required before a frame as described in
the IEEE standard. At the rising edge of RSTB, the
S19252 loads the device address into a register from
the ADDRESS[4:0] pins and uses it to decode
accesses to its registers. The ADDRESS[4:0] default is
defined by the user. These address bits are used to
uniquely identify each S19252 device if multiple
S19252
microprocessor. Because there are five address lines,
2
single microprocessor. A frame is formatted as shown
in Table 17.
Start of frame: Start of frame is indicated by 01
pattern.
Operation code: For read transaction, 10; For write
transaction, 01.
32
5
= 32 S19252 devices that can be configured by a
The S19252 has a unique address on the bus and
a simple master/slave relation exists at all times.
Only two bus lines are required; a Management
Data Input/Output line (MDIO) and a Management
Data Control line (MDC). All address/data (MDIO)
bits to the S19252 and read data (MDIO) bits for
the host are sampled on the rising edge of the
clock (MDC).
devices
Interface
are
standard.
controlled
AppliedMicro - Confidential and Proprietary
Communication
by
a
single
Device Address: The S19252 compares the five
address bits of device address to the latched address
bits (see Table 17). If they are equal, the S19252
proceeds with the access. If they are not equal, the
S19252 ignores the access and does not drive the
MDIO signal.
Register address: This field is used to select the
registers to be accessed. The register address is 8 bits.
The upper 3 page address bits MDIO_PAGE[2:0] are
located in register 0x00 bits [7:5]. The remaining lower
5 register address bits are within the MDIO frame
shown below as RRRRR. To find the current MDIO
register page address read register address 0x00. The
page address may be changed while in any page.
When accessing register address range from 0x20 to
0x9C use the MDIO_PAGE[2:0] pointer bits to address
the upper pages. At power up the MDIO_PAGE pointer
will default to page 0x00 for address range 0x00 to
0x1F.
Turnaround: The two bits between address field and
data field are used to avoid contention on the MDIO
during a read transaction. For a read transaction,
MDIO should be in tri-state for the first cycle of the
turnaround. The S19252 drives zero during the second
cycle of the turnaround. For a write transaction, the
system should drive one during the first cycle of the
turnaround and zero during the second cycle of the
turnaround.
Data field: Bits 15:8 are always zero. Bits 7:0 contain
the contents of the selected register. On reads,
reserved register bits will be zero. The first bit
transmitted is bit 15.
Idle condition: A final clock puts MDIO back in an idle
state (MDIO is tri-stated and pulled-up).
Revision 5.03