S19252PBIDB Applied Micro Circuits Corporation, S19252PBIDB Datasheet - Page 29

• Manufacturer Part Number: S19252PBIDB
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S19252PBIDB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Receive Built-In Self Test Mode
The S19252 circuitry includes a PRBS generator and a
checker. The receive built-in self test allows for the
verification of the parallel input and output data paths in
the S19252. The S19252 goes in the receive BIST
mode when RX_BIST_EN is programmed to logic high.
Once the S19252 is in the receive BIST mode, the
PRBS generator will start sending the pattern through
the parallel output data path. The pattern can be a
PRBS pattern or a user defined pattern depending
upon the PRBS_SELECT[1:0] settings. See Table 13
for details. The user defined pattern can be loaded
through the BIST_PTRN[15:0] register. There are two
modes of receive BIST operation:
When the line loopback mode is not active, the parallel
output data (POUTP/N[15:0]) must be looped back
externally into the parallel input (PINP/N[15:0]) for the
receive PRBS checker to work with the receive PRBS
generator. If the line loopback mode is enabled, the
POUTP/N[15:0] outputs will be internally looped back
into the PINP/N[15:0] inputs.
Once the RX_BIST_EN input is programmed to logic
high, the receive PRBS checker will be activated but
will not start checking for the valid data pattern until
TX_LOCKDET is active. This ensures that valid data is
being passed through the receive channel. Once the
TX_LOCKDET is active, the checker will begin its
initialization phase for 15 CRU_REFCLK cycles. The
receive checker reads the parallel data output and
figures out the next pattern in the initialization phase.
After the checker is initialized, it will compare the
parallel data input with the calculated pattern. If the
parallel data input does not match the calculated
pattern, the RX_BIST_ERR flag will be set active and
the number of errors will start accumulating on the
BER_COUNT[11:0] register. The bit error rate range
Revision 5.03
1. Normal operation with LLEB disabled
2. Normal operation with LLEB enabled
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can be selected with the appropriate setting of the
BER_SELECT[2:0]. See Table 14 for details of setting
the range for bit error rate.
The RX_BIST_ERR flag can be cleared by asserting
RX_BIST_CLR in the RX_BIST_EN mode or by
resetting (RSTB) the S19252. Once the RX_BIST_CLR
signal has been received by the checker, it will go back
to the initialization phase. RX_BIST_CLR is an active
high level sensitive input. In order for the checker to
clear the RX_BIST_ERR flag, the RX_BIST_CLR must
be asserted high.
Also the BER_RSTB input register resets the
BER_COUNT[11:0]
BER_RSTB is a active high input. When active
BER_COUNT[11:0] is not reset after each terminal
count, but instead continues to accrue errors. When
inactive, BER_COUNT[11:0] is reset to zero error value
after each terminal count. The TERM_COUNT output
monitors for the terminal count of the PRBS checker.
The terminal count is set by the BER_SELECT[2:0]
register. See Table 14 for details. Each transition of
TERM_COUNT signal indicates that the terminal count
has been reached. This signal is initially set low upon
RSTB
activated. The TERM_COUNT makes a low to high
transition when the first terminal count is reached. A
transition
BER_COUNT[11:0] register to zero depending upon
the BER_RSTB setting. When BER_RSTB is active
(high), BER_COUNT[11:0] is not reset after each
terminal count, but instead continues to accrue errors.
The BER_OVERFLOW output will indicate if the
BER_COUNT[11:0]
BER_OVERFLOW goes active, the bit error rate range
select (BER_SELECT[2:0]) needs to be changed. This
signal is active high and is latched high. This signal
monitors the RX checker count when the RX_BIST_EN
is active and TX checker count when TX_BIST_EN is
active.
or
on
when
TERM_COUNT
TX_BIST_EN/RX_BIST_EN
has
after
overflowed.
each
S19252 Data Sheet
terminal
will
When
set
count.
are
the
the
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