S19252PBIDB Applied Micro Circuits Corporation, S19252PBIDB Datasheet - Page 51

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S19252PBIDB

Manufacturer Part Number
S19252PBIDB
Description
Manufacturer
Applied Micro Circuits Corporation
Datasheet

Specifications of S19252PBIDB

Lead Free Status / Rohs Status
Supplier Unconfirmed
Table 23: Output Pin Assignments and Descriptions
Revision 5.03
TSDP
TSDN
TSCLKP
TSCLKN
PCLKP
PCLKN
TX_155MCKP
TX_155MCKN
TX_LOCKDET
PHERR
PD_UPP
PD_UPN
PD_DWNP
PD_DWNN
TX_BIST_ERR
Pin Name
& Regis-
Register
Register
diff CML
diff CML
Pull Up
CMOS
Detec-
tor Diff
Speed
Speed
0x82h
Phase
0x86h
Level
LVDS
LVDS
High
High
CML
LV
ter
AppliedMicro - Confidential and Proprietary
I/O
O
O
O
O
O
O
O
O
Pin#
D10
E10
J15
G1
D1
D7
B1
B9
A9
A8
B8
E7
J1
Transmitter Outputs
Transmit Serial Data. Serial data stream signals, normally con-
nected to an optical transmitter module. Output return loss, S
-12dB at 15 GHz.
Transmit Serial Clock. Serial clock signals, normally connected to a
lab test equipment or an optical laser module.
Parallel Clock. A 622.08 MHz (or equivalent FEC/10 Gigabit Ether-
net rate) reference clock. It is normally used to coordinate data trans-
fers between upstream logic and the S19252 device.
155.52 MHz Clock Output. 155.52 MHz (or equivalent FEC/10 GbE/
10 G FC rates) clock output from CSU_REFCLK. The output can be
connected to the reference clock input (CRU_REFCLKP/N) of the
clock recovery function.
Transmit Lock Detect. Active high. Goes active after the PLL has
locked to the clock provided on the CSU_REFCLK pins.
TX_LOCKDET is an asynchronous output.
Phase Error. Pulses high during each PCLK cycle for which there is
a potential FIFO overrun/underrun condition. No additional external
components required. Should be directly connected to PHINIT
through serial bus register.
Phase Detector Output. This output is used to drive an external
charge pump which, in turn, drives the external VCO. The external
VCO output is then fed into the CSU_INP/N input to be used as the
transmit reference clock for the CSU block.
Transmit Built-In Self Test Error. This output indicates a bit error in
the transmit built-in self test loop.
Description
S19252 Data Sheet
22
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