S19252PBIDB Applied Micro Circuits Corporation, S19252PBIDB Datasheet - Page 47

• Manufacturer Part Number: S19252PBIDB
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S19252PBIDB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 22: Input Pin Assignments and Descriptions (Continued)
Revision 5.03
TAP[2:0]_CNTL
CSU_INP
CSU_INN
TXPD
TX_DATA_SWAP
LVDS_INPUT_AC_EN
SERDATIP
SERDATIN
CENTER_TAP
PAOFFADJ9
PAOFFADJ8
PAOFFADJ7
PAOFFADJ6
PAOFFADJ5
PAOFFADJ4
PAOFFADJ3
PAOFFADJ2
PAOFFADJ1
PAOFFADJ0
ADAPOFFADJ
Pin Name
0x0B-0Ch
LVCMOS
REFCLK
Diff CML
Diff CML
Register
Register
Register
Register
Register
Analog
Speed
0x0Bh
0x03h
0x34h
0x19h
0x18h
Level
Down
High
Pull
AppliedMicro - Confidential and Proprietary
I/O
I
I
I
I
I
I
I
I
I
Pin#
B7
A7
E9
R1
U1
N1
Receiver Inputs
Transmitter De-Emphasis 3 Tap FIR Filter. This feed forward equal-
ization control on the transmitter output provides additional gain to
compensate for dispersion losses in FR4. TAP0 and TAP2 each have
an adjustment range of 0 to 16. TAP1 provides no adjustment.
(Default: TAP0 = 0, TAP2 = 3)
Clock Synthesizer Input. Input to the internal CSU. Used to gener-
ate the serial transmit data. This input is internally biased and termi-
nated. This input must be AC coupled.
Transmitter Power Down. (Active high) For transmitter power down
set to logic 1 (high) when S19252 is used as receiver.
Parallel Input Data Bus Reversal. Reverses the order of the parallel
input data bus (PINP/N[15:0]). TX_DATA_SWAP input should be pro-
grammed to logic low (Default) when S19252 is used with 300-pin
MSA connector. TX_DATA_SWAP input should be programmed to
logic high when S19252 is used with 200-pin MSA connector. This
signal can be accessed through the serial bus register (Default = 0).
LVDS Input AC Enable. When enabled provides input bias for AC
coupled LVDS (PINP/N[15:0] and PICLKP/N) inputs. When (PINP/
N[15:0] and PICLKP/N) inputs are DC coupled this control must be
disabled to allow DC input level shifting circuit operation. This control
can be accessed through serial bus register (Default = 1).
Serial Data Input. Differential high-frequency serial data input to limit-
ing post-amp for small signal gain. Internally biased and terminated
100  line-to-line (5050 with center tap capacitor. This input
must be AC coupled.
Center Tap Input. This input should be connected to a broadband
0.01 F capacitor to ground.
Post-Amp Offset Adjust. Used to correct duty cycle distortion on the
input data signal. See Table 9 for details. This signal can be accessed
through the serial bus register. The default state will depend up on the
fuse settings and may vary from one device to another.
Adaptive Post-Amp Offset Adjust Enable. Enables the adaptive
offset adjustment control. See Table 10 for details. This signal can be
accessed through the serial bus register (Default = 1).
Description
S19252 Data Sheet
47