S19252PBIDB Applied Micro Circuits Corporation, S19252PBIDB Datasheet - Page 16

• Manufacturer Part Number: S19252PBIDB
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S19252PBIDB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

S19252 Data Sheet
Lock-to-Reference (LCKREFN) –
Register
The active low Lock-to-Reference (LCKREFN) input
register, when asserted low, will force the PLL to lock to
the Reference Clock defined by the RXREFSEL and
de-assert RX_LOCKDET. The POCLKP/N will lock to
the reference clock in this mode. When the LCKREFN
is inactive (high), the POCLKP/N will lock to the valid
incoming serial data (SERDATIP/N). This input should
be programmed to logic high for normal operation. This
input is only accessible through the serial bus register.
LOS/Signal Detect (LOS_SD) – External
Pin
This is a dual-purpose pin that can be either an input or
output pin, the I/O function is controlled by setting
LOS_SDC bit via serial bus. When the LOS_SDC is set
to ‘0’, this pin will be a Signal Detect input pin. The
default of this pin is a Signal-Detect input pin.
The Signal-Detect is an active high or active low
LVCMOS single-ended input to be driven by the
external optical receiver module to indicate the
presence of received optical power. Signal Detect
active level (high or low) is programmed by the
SD_POL.
As an output pin, by setting the LOS_SDC to ‘1’ and
the RX_LOS_CNTL to ‘1’, this pin will act as a Loss-of-
Signal (LOS) output pin. When the SD_POL is set to
‘1’, the LOS_SD will be active high.
When a loss-of-light condition occurs, a de-asserted
Signal-Detect (LOS_SD) input pin or an asserted Loss-
of-Signal (LOS_SD) output pin will cause the internal
PLL to be locked to the CRU reference input signal and
if, the squelch function is enabled (default), the
SERDATIP/N (and POUT[15:0]) will be forced to a
Logic ‘0’ state.
Signal Detect Polarity (SD_POL) –
Register
The signal detect polarity is an input signal that will set
the LOS_SD input as either active high or active low.
Setting this pin low will set the LOS_SD input as active
low. Setting this pin high will set the LOS_SD input as
active high. This input is only accessible through the
serial bus register.
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RX Ref. Select (RXREFA_NOTB) –
Register
The RX Reference Select (RXREFA_NOTB) input
selects
reference clock input. When the RXREFA_NOTB is set
low (default), the REFCLKBP/N is selected to be the
input for the Receiver Reference Frequency for the
Clock Data Recover Unit (CRU). When this bit is set
high, the REFCLKAP/N is used as the CRU reference
frequency input. This input is only accessible through
the serial bus registers.
Table 5:
Receive Reference Rate Select
(RXREFSEL) – Register
This is the receive reference rate select input. When
SONET_RATESEL is low, and GBE_RATESEL is high
denotes that the 10 GE reference (156.25 MHz) or FC
reference
SONET_RATESEL is high, the RXREFSEL low
indicates that the 155 MHz clock is used; and while
high 622 MHz clock is used. See Table 6. This input is
only accessible through the serial bus register.
Table 6:
Note that the source of RXREFCLK is either REFCLKA or
REFCLKB. The default is REFCLKBP/N.
RXREFA_NOTB
REF
SEL
RX
X
0
1
1
0
between
SONET_
Receive Reference Source Select
Receive Reference Rate Select
RATE
SEL
(159.375 MHz)
0
1
1
REFCLKAP/N
GBE_
RATE
SEL
X
X
1
Reference Clock Source
REFCLKBP/N (Default)
REFCLKAP/N
155 (or equiv. FEC rate)
622 (or equiv. FEC rate)
159.375 (or equiv. FEC
(10GE) 156.25 or (FC)
is
Reference Clock
(MHz) and Rate
or
Multiplier
rate) x66
used.
x64
x16
REFCLKBP/N
Revision 5.03
When