S19252PBIDB Applied Micro Circuits Corporation, S19252PBIDB Datasheet - Page 34

• Manufacturer Part Number: S19252PBIDB
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S19252PBIDB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

S19252 Data Sheet
I
S19252 has the option to use a simple I
directional two-wire bus for efficient inter-IC control. All
register
programmed via the I
description can found in the S19252 Programming
Manual.
The following are some important features of I
BUS
•
•
•
The serial port interface is based on the I
Communication occurs across two wires and is
formatted in frames. The two wires are clock (SCL) and
data (SDA). At the rising edge of RSTB, the S19252
Figure 6:
34
2
C BUS
The S19252 has a unique I
upper 4 bits[7:4] fix at 1101 and bits [3:1] the
device ADDRESS[2:0] bits (see Table 16).
The S19252 I
configuration at all times.
Only two bus lines are required; a serial Data Input/
Output line (SDA) and a Clock line (SCL).
®
:
controlled
Two Wire Slave Address
®
and Address Register
MSB
2
C interface operates as a slave
1
2
C BUS
features
1
®
AppliedMicro - Confidential and Proprietary
. A detailed register map
2
C address with the
and
7-bit slave address
0
functions
1
2
C bi-
Device ADDRESS[2:0]
are
2
2
C.
C
X
loads the device address into a register from the device
ADDRESS[2:0] pins and uses it to decode access to its
I
ups are connected to these bits. The address bits are
used to uniquely identify the S19252 device if multiple
I
A frame is formatted as shown in Figure 6.
I
during SCL high time.
I
the receiver after a data transfer.
I
the receiver after a data transfer.
Stop Code:
After this condition, the bus becomes tristated, and both SDA
and SCL are pulled high.
REFCLKP/N is not required for read/write registers
access through the I
2
2
2
2
2
C port. The ADDRESS[2:0] default is 000 if no pull
C devices are controlled by a single microprocessor.
C Start/Repeat Conditions: A falling edge on SDA
C Acknowledge:
C Not Acknowledge: A high left on the SDA line by
X
A rising edge on SDA during SCL high time.
X
A low assertion on the SDA line from
2
C interface.
W=0
LSB ACK
R/W
R=1
Revision 5.03