S19252PBIDB Applied Micro Circuits Corporation, S19252PBIDB Datasheet - Page 25

• Manufacturer Part Number: S19252PBIDB
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S19252PBIDB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Clock Synthesizer
The clock synthesizer shown in the block diagram in
Figure 5, is a monolithic PLL that generates the serial
output clock frequency locked to the input Reference
Clock (CSU_REFCLKP/N).
The CSU_REFCLKP/N input must be generated from a
crystal oscillator which has a frequency accuracy that
meets the value stated in Table 27 in order for the
Transmit Serial Data (TSDP/N) frequency to have the
accuracy required for operation in a SONET/10 Gigabit
Ethernet system. The CSU_REFCLK must also meet
the phase noise requirements shown in Figures 18 and
20 in order to meet the jitter generation specifications
as defined in GR-253-CORE. Lower accuracy crystal
oscillators may be used in applications less demanding
than the SONET/SDH.
The on-chip PLL consists of; a phase detector, which
compares the phase relationship between the VCO
output and the CSU_REFCLK input, a loop filter, which
converts the phase detector output into a smooth DC
voltage, and a VCO, whose frequency is varied by this
voltage.
The loop filter generates a VCO control voltage based
on the average DC level of the phase discriminator
output pulses. A single external clean-up capacitor is
utilized as part of the loop filter. The loop filter’s corner
frequency is optimized to minimize output phase jitter.
Loop Timing
In Reference Loop Timing mode (RLPTIME), the
Parallel Clock (POCLK) from the receiver is used as
the reference clock to the transmitter. In this mode, the
CSU_REFCLKP/N input is not used. The TX_155MCK
is generated from the POCLK in this operating mode.
When operating the S19252 in RLPTIME mode, the
TX_155MCK output should not be used as the backup
reference clock (CRU_REFCLK) for the clock recovery
unit. When performing loopback testing (DLEB), the
S19252 must not be in RLPTIME mode.
The XVCO input should be programmed to logic high in
the
recommended to be used in the RLPTIME mode. The
internal POCLK will be fed into the external tracking
filter (filter and VCO) for cleanup in the RLPTIME
mode. The output of the external VCO (which is fed
into the CSU_IN input) will be used as the reference
clock for the CSU.
Revision 5.03
RLPTIME
mode.
The
AppliedMicro - Confidential and Proprietary
external
VCO
is
If the external VCO is not used in RLPTIME mode the
jitter present from the CRU received data will be
passed through to the transmitter.
Line Loopback
The line loopback circuitry selects the source of the
data that is output on the TSD. When the Line
Loopback Enable (LLEB) input is inactive (high), it
selects data and clock from the parallel-to-serial
converter block. When LLEB is active (low), it forces
the output data multiplexer to select the data from the
RSD
loopback can be established at the serial data rate. The
parallel data outputs POUT[15:0] and parallel output
clock POCLK are accessible in the LLEB mode.
Timing Generator
The timing generator function, shown in the block
diagram in Figure 5, Transceiver Functional Block
Diagram, provides a 16-bit parallel rate clock output.
The PCLK output is a 16-bit parallel clock. For
192, the PCLK frequency is 622.08 MHz. PCLK is
intended for use as a 16-bit parallel speed clock for
upstream
circuits. Using PCLK for upstream circuits will ensure a
stable frequency and phase relationship between the
data coming into and leaving the S19252 device.
In the parallel-to-serial conversion process, the
incoming data is passed from the PICLK clock timing
domain to the internally generated PCLK clock timing
domain.
The timing generator also produces a feedback
reference clock to the clock synthesizer. A counter
divides the synthesized clock down to the same
frequency
(CSU_REFCLK). The PLL in the clock synthesizer
maintains the stability of the synthesized clock by
comparing the phase of the feedback clock with that of
the CSU_REFCLK. The modulus of the counter is a
function of the reference clock frequency.
(internal)
multiplexing
as
the
input,
Transmit
and
and
overhead
a
S19252 Data Sheet
Reference
receive-to-transmit
processing
Clock
STS-
25