S19252PBIDB Applied Micro Circuits Corporation, S19252PBIDB Datasheet - Page 35

• Manufacturer Part Number: S19252PBIDB
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S19252PBIDB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Serial Peripheral Interface (SPI)
S19252 has the option to use a simple SPI bi-
directional serial bus for efficient inter-IC control. All
register
programmed via the SPI bus. A detailed register map
description can found in the S19252 Programming
Manual. The SPI bus is a simple communications
system with a master which shifts data into the slave
while the slave simultaneously shifts data out. Serial
EEPROM manufactures have developed a defacto
standard protocol for write and reads over SPI that will
be supported by the SPI. SPI as defined uses two pins
to define the operating mode: CPOL (clock polarity)
and CPHA (clock phase). Of the four combinations of
these two signals, two of the modes are supported by
most serial EEPROMs:
mode 0, 0; (CPOL = 0, CPHA = 0)
mode 1, 1; (CPOL = 1, CPHA = 1)
The SPI will support modes 0, 0 and 1, 1. From a slave
point of view both modes are identical when using the
standard protocol, in that the data is sampled on the
rising edge of the clock and presented on the falling
edge of the clock.
The SPI interface operates at a SPI_SCK frequency up
to 10 MHz.
SPI Pin Signals
spi_sck: Clock (SCK). The spi_sck pin is an input that
synchronizes the data transfer between the master and
slave devices. Slave devices ignore the spi_sck signal
unless the slave select pin (spi_cs_n) is active (low)
and spi_hold_n is inactive (high). In both supported
modes for both the master and slave SPI devices, data
is shifted out on the falling edge of the spi_sck signal
and is sampled on the rising edge where data is stable.
spi_sdo: Slave Data Out (also referred to as MISO -
Master In Slave Out).
Revision 5.03
controlled
features
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and
functions
are
spi_sdi: Slave Data In (also referred to as MOSI -
Master Out Slave In).
spi_cs_n: Slave Chip Select (CS_n). This pin is used
to enable the SPI slave for a transfer. If the spi_cs_n
pin of a slave is inactive (high), the device ignores
spi_sck clocks and keeps the spi_sdo output pin in the
high-impedance state.
spi_cpol: Clock Polarity (CPOL). The clock polarity pin
is used to select either an active high clock (spi_cpol =
1) or active low clock (spi_cpol= 0). This pin is not
present in this implementation.
SPI Protocol
Register reads and writes will follow a protocol similar
to SPI implementations for serial EEPROMs. Read and
write transfers are at least three bytes in length with the
first byte containing the 2-bit read or write opcode, the
second byte containing the register address, and the
third byte the write data or returned read data.
Multi-byte reads and writes are accomplished by simply
continuing to write (or read) bytes while spi_cs_n
remains active. If autoinc_en is set the register address
is automatically incremented after each write or read.
The chip select line spi_cs_n must go active before the
transfer begins and must go inactive after the transfer
ends. To maintain this protocol spi_cs_n cannot remain
or be tied active low. This requirement differs from
allowable spi_cs_n behavior when CPHA= 1 in the
original SPI specification.
The READ opcode is 00000011b and the WRITE
opcode is 00000010b. A detected invalid opcode will
result in no registers being written and the spi_so
output will remain high Z.
JTAG Interface
To perform JTAG operations, RSTB must be pulsed
low prior to JTAG testing or RSTB must be held low for
the duration of the JTAG usage.
S19252 Data Sheet
35