MT48LC8M32B2P-6 Micron Technology Inc, MT48LC8M32B2P-6 Datasheet - Page 6

• Manufacturer Part Number: MT48LC8M32B2P-6
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC8M32B2P-6

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/7.5/5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 165mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

256Mb (x32) SDRAM Part Number
General Description
The 256Mb SDRAM is a high-speed CMOS, dynamic
random-access memory containing 268,435,456-bits.
It is internally configured as a quad-bank DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the
67,108,864-bit banks is organized as 4,096 rows by 512
columns by 32 bits.
Read and write accesses to the SDRAM are burst ori-
ented; accesses start at a selected location and con-
tinue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed
(BA0, BA1 select the bank, A0–A11 select the row). The
address bits registered coincident with the READ or
WRITE command are used to select the starting col-
umn location for the burst access.
09005aef8140ad6d
MT48LC8M32B2_2.fm - Rev. B 10/04 EN
MT48LC8M32B2TG
MT48LC8M32B2B5
MT48LC8M32B2F5
MT48LC8M32B2P
PART NUMBER
ARCHITECTURE
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
90-ball FBGA
90-ball FBGA
86-pin TSOP
86-pin TSOP
PACKAGE
6
The SDRAM provides for programmable READ or
WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence.
The 256Mb SDRAM uses an internal pipelined archi-
tecture to achieve high-speed operation. This architec-
ture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging 1 bank while
accessing one of the other 3 banks will hide the pre-
charge cycles and provide seamless, high-speed, ran-
dom-access operation.
The 256Mb SDRAM is designed to operate in 3.3V
memory systems. An auto refresh mode is provided,
along with a power-saving, power-down mode. All
inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operat-
ing performance, including the ability to synchro-
nously burst data at a high data rate with automatic
column-address generation, the ability to interleave
between internal banks to hide precharge time and the
capability to randomly change column addresses on
each clock cycle during a burst access.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x32
SDRAM