MT48LC8M32B2P-6 Micron Technology Inc, MT48LC8M32B2P-6 Datasheet - Page 37

• Manufacturer Part Number: MT48LC8M32B2P-6
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC8M32B2P-6

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/7.5/5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 165mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Notes
09005aef8140ad6d
MT48LC8M32B2_2.fm - Rev. B 10/04 EN
10.
11. AC timing and I
1. All voltages referenced to V
2. This parameter is sampled. V
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
6. An initial pause of 100µs is required after power-
7. AC characteristics assume
8. In addition to meeting the transition rate specifi-
9. Outputs measured at 1.5V with equivalent load:
1 MHz, T
can range from 0pF to 6pF.
rates. Specified values are obtained with mini-
mum cycle time and the outputs open.
indicate cycle time at which proper operation
over the full temperature range (0°C ≤ T
and -40°C ≤ T
up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (V
and V
V
AUTO REFRESH command wake-ups should be
repeated any time the
exceeded.
cation, the clock and CKE must transit between
V
tonic manner.
t
the open circuit condition; it is not a reference to
V
t
2.75, with timing referenced to 1.5V crossover
point.
HZ defines the time at which the output achieves
OH before going High-Z.
DD
OH
SS
IH
and V
and V
is dependent on output loading and cycle
or V
DD
OL
A
Q must be powered up simultaneously.
SS
IL
= 25°C; pin under test biased at 1.4V. AC
. The last valid data element will meet
Q must be at same potential.) The two
(or between V
A
Q
≤ +85°C for IT parts) is ensured.
DD
tests have V
t
REF refresh requirement is
t
IL
SS
T = 1ns.
.
DD
and V
, V
IL
DD
30pF
=.25 and V
IH
Q = +3.3V; f =
) in a mono-
A
≤ +70°C
IH
DD
=
37
12. Other input signals are allowed to transition no
13. I
14. Timing actually specified by
15. Timing actually specified by
16. Timing actually specified by
17. Required clocks are specified by JEDEC function-
18. The I
19. Address transitions average one transition every
20. CLK must be toggled a minimum of two times
21. Based on
22. V
23. The clock frequency must remain constant during
24. Auto precharge mode only.
25. JEDEC and PC100 specify three clocks.
26.
27. Check factory for availability of specially screened
more than once in any two-clock period and are
otherwise at valid V
properly initialized.
fied as a reference only at minimum cycle rate.
specified as a reference only at minimum cycle
rate.
ality and are not dependent on any timing param-
eter.
This is due to the fact that the maximum cycle rate
is slower as CL is reduced.
two clocks.
during this period.
pulse width ≤ 3ns, and the pulse width cannot be
greater than one third of the cycle rate. V
shoot: V
and the pulse width cannot be greater than one
third of the cycle rate.
access or precharge states (READ, WRITE, includ-
ing
be used to reduce the data rate.
t
devices having
MHz and slower (
ual precharge.
CK = 7ns for -7; 6ns for -6.
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IH
t
specifications are tested after the device is
overshoot: V
WR and PRECHARGE commands). CKE may
DD
IL
current will decrease as CL is reduced.
t
CK = 143 MHz for -7; 166 MHz for -6.
(MIN) = -1.2V for a pulse width ≤ 3ns,
t
WR = 10ns.
IH
t
CK = 10ns and higher) in man-
IH
(MAX) = V
or V
©2003 Micron Technology, Inc. All rights reserved.
IL
levels.
t
t
256Mb: x32
WR plus
WR.
t
t
WR = 1
CKS; clock(s) speci-
DD
Q + 1.2V for a
SDRAM
t
RP; clock(s)
t
CK for 100
IL
under-