MT48LC8M32B2P-6 Micron Technology Inc, MT48LC8M32B2P-6 Datasheet - Page 23

• Manufacturer Part Number: MT48LC8M32B2P-6
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC8M32B2P-6

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/7.5/5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 165mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Data for any WRITE burst may be truncated with a
subsequent READ command, and data for a fixed-
length WRITE burst may be immediately followed by a
READ command. Once the READ command is regis-
tered, the data inputs will be ignored, and WRITEs will
not be executed. An example is shown in Figure 20.
Data n + 1 is either the last of a burst of two or the last
desired of a longer burst.
Data for a fixed-length WRITE burst may be followed
by, or truncated with, a PRECHARGE command to the
same bank (provided that auto precharge was not acti-
vated), and a full-page WRITE burst may be truncated
with a PRECHARGE command to the same bank. The
PRECHARGE command should be issued
clock edge at which the last desired input data element
is registered. The two-clock write-back requires at least
one clock plus time, regardless of frequency, in auto
precharge mode.
In addition, when truncating a WRITE burst, the DQM
signal must be used to mask input data for the clock
edge prior to, and the clock edge coincident with, the
PRECHARGE command. An example is shown in
Figure 21 on page 24. Data n + 1 is either the last of a
burst of two or the last desired of a longer burst. Fol-
lowing the PRECHARGE command, a subsequent
command to the same bank cannot be issued until
is met. The precharge will actually begin coincident
with the clock-edge (T2 in Figure 21) on a one-clock
t
on a two-clock
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the
command and address buses be available at the
appropriate time to issue the command; the advantage
of the PRECHARGE command is that it can be used to
truncate fixed-length or full-page bursts.
Fixed-length or full-page WRITE bursts can be trun-
cated with the BURST TERMINATE command. When
truncating a WRITE burst, the input data applied coin-
cident with the BURST TERMINATE command will be
09005aef8140ad6d
MT48LC8M32B2_2.fm - Rev. B 10/04 EN
WR and sometime between the first and second clock
t
WR (between T2 and T3 in Figure 21.)
t
WR after the
t
RP
23
ignored. The last data written (provided that DQM is
LOW at that time) will be the input data applied one
clock previous to the BURST TERMINATE command.
This is shown in Figure 22, where data n is the last
desired data element of a longer burst.
NOTE:
NOTE:
COMMAND
ADDRESS
Each WRITE command may be to any bank. DQM is
LOW.
The WRITE command may be to any bank, and the
READ command may be to any bank. DQM is LOW.
CL = 2 for illustration.
Figure 19: Random WRITE Cycles
Micron Technology, Inc., reserves the right to change products or specifications without notice.
COMMAND
CLK
DQ
ADDRESS
Figure 20: WRITE to READ
CLK
DQ
WRITE
BANK,
COL n
D
T0
n
IN
BANK,
WRITE
COL n
D
T0
n
IN
n + 1
NOP
T1
D
IN
WRITE
BANK,
COL a
T1
D
a
IN
BANK,
READ
COL b
T2
©2003 Micron Technology, Inc. All rights reserved.
BANK,
WRITE
COL x
T2
D
x
IN
T3
NOP
256Mb: x32
WRITE
COL m
BANK,
T3
D
m
IN
DON’T CARE
NOP
SDRAM
D
T4
OUT
b
DON’T CARE
NOP
b + 1
T5
D
OUT