MT48LC8M32B2P-6 Micron Technology Inc, MT48LC8M32B2P-6 Datasheet - Page 15

• Manufacturer Part Number: MT48LC8M32B2P-6
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC8M32B2P-6

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/7.5/5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 165mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Once the SELF REFRESH command is registered, all
the inputs to the SDRAM become “Don’t Care” with the
exception of CKE, which must remain LOW.
Once self refresh mode is engaged, the SDRAM pro-
vides its own internal clocking, causing it to perform
its own AUTO REFRESH cycles. The SDRAM must
remain in self refresh mode for a minimum period
equal to
an indefinite period beyond that.
The procedure for exiting self refresh requires a
sequence of commands. First, CLK must be stable (sta-
ble clock is defined as a signal cycling within timing
constraints specified for the clock pin) prior to CKE
going back HIGH. Once CKE is HIGH, the SDRAM
must have NOP commands issued (a minimum of two
clocks) for
pletion of any internal refresh in progress.
Upon exiting self refresh mode, AUTO REFRESH com-
mands must be issued every 15.625µs or less as both
SELF REFRESH and AUTO REFRESH utilize the row
refresh counter.
Operations
Bank/Row Activation
Before any READ or WRITE commands can be issued
to a bank within the SDRAM, a row in that bank must
be “opened.” This is accomplished via the ACTIVE
command, which selects both the bank and the row to
be activated. See Figure 6.
After opening a row (issuing an ACTIVE command), a
READ or WRITE command may be issued to that row,
subject to the
be divided by the clock period and rounded up to the
next whole number to determine the earliest clock
edge after the ACTIVE command on which a READ or
WRITE command can be issued. For example, a
specification of 20ns with a 143 MHz clock (7ns
period) results in 2.5 clocks, rounded to three. This is
reflected in Figure 7, which covers any case where 2 <
t
convert other specification limits from time units to
clock cycles.) A subsequent ACTIVE command to a dif-
ferent row in the same bank can only be issued after
the previous active row has been closed (precharged).
The minimum time interval between successive
ACTIVE commands to the same bank is defined by
09005aef8140ad6d
MT48LC8M32B2_2.fm - Rev. B 10/04 EN
RCD (MIN)/
t
RAS and may remain in self refresh mode for
t
XSR because time is required for the com-
t
CK - 3. (The same procedure is used to
t
RCD specification.
t
RCD (MIN) should
t
RCD
t
RC.
15
A subsequent ACTIVE command to another bank can
be issued while the first bank is being accessed, which
results in a reduction of total row-access overhead. The
minimum time interval between successive ACTIVE
commands to different banks is defined by
Figure 6: Activating a Specific Row in a
Figure 7: Example: Meeting
NOTE:
COMMAND
t
t
tion to be true.
RCD (MIN) = 20ns,
RCD (MIN) x
BA0, BA1
CLK
Micron Technology, Inc., reserves the right to change products or specifications without notice.
A0-A11
RAS#
CAS#
When 2 <
WE#
CLK
CKE
CS#
ACTIVE
T0
t
HIGH
CK where x = number of clocks for equa-
t CK
Specific Bank
t
CK = 7ns
t
RCD (MIN)/
t
t RCD (MIN) +0.5 t CK
NOP
RCD (MIN)
T1
©2003 Micron Technology, Inc. All rights reserved.
t CK
ADDRESS
ADDRESS
BANK
ROW
256Mb: x32
NOP
T2
t
CK - 3
DON´T CARE
t
RCD (MIN)
SDRAM
t CK
t
RRD.
READ or
DON’T CARE
WRITE
T3