MT48LC8M32B2P-6 Micron Technology Inc, MT48LC8M32B2P-6 Datasheet - Page 11

• Manufacturer Part Number: MT48LC8M32B2P-6
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC8M32B2P-6

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/7.5/5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 165mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Burst Type
Accesses within a given burst may be programmed to
be either sequential or interleaved; this is referred to as
the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined
by the burst length, the burst type and the starting col-
umn address, as shown in Table 4.
NOTE:
09005aef8140ad6d
MT48LC8M32B2_2.fm - Rev. B 10/04 EN
1. For BL = 2, A1–A8 select the block-of-two burst; A0 selects the starting column within the block.
2. For BL = 4, A2–A8 select the block-of-four burst; A0–A1 select the starting column within the block.
3. For BL = 8, A3–A8 select the block-of-eight burst; A0–A2 select the starting column within the block.
4. For a full-page burst, the full row is selected and A0–A8 select the starting column.
5. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the
6. For BL = 1, A0–A8 select the unique column to be accessed, and mode register bit M3 is ignored.
*Should be
programmed
to “0” to ensure
compatibility with
future devices.
Figure 4: Mode Register Definition
block.
13
BA1
Reserved*
12
BA0
11
A11
10
A10
WB
M9
0
1
9
A9
Op Mode
8
A8
7
A7
Programmed Burst Length
CAS Latency
M8
0
Single Location Access
-
6
Write Burst Mode
A6
5
M7
A5
0
-
4
A4
BT
M3
M6 - M0
Defined
0
1
3
A3
-
M6
M2
Burst length
0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
2
A2
M5
M1
0
M4
M0
1
Operating Mode
Standard operation
All other states reserved
A1
0
A0
Reserved
Reserved
Reserved
Full Page
M3 = 0
0
Burst Type
Sequential
Interleave
1
2
4
8
Mode Register (Mx)
Address Bus
Burst Length
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
1
2
3
Reserved
Reserved
Reserved
Reserved
M3 = 1
1
2
4
8
11
Table 4:
LENGTH
BURST
(512)
Page
Full
2
4
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
A2
0
0
0
0
1
1
1
1
STARTING
ADDRESS
n = A0–A8
COLUMN
(Location
0–511)
Burst Definition
A1
A1
0
0
1
1
0
0
1
1
0
0
1
1
A0
A0
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Cn + 2, Cn + 3,
ORDER OF ACCESSES WITHIN
SEQUENTIAL
Cn, Cn + 1,
Cn + 4...
TYPE =
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
...Cn-1,
©2003 Micron Technology, Inc. All rights reserved.
Cn...
0-1
1-0
256Mb: x32
A BURST
INTERLEAVED
Not Supported
SDRAM
TYPE =
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0