Z84C3006PEG Zilog, Z84C3006PEG Datasheet - Page 82
![IC 6MHZ Z80 CMOS CTC 28-PDIP](/photos/6/57/65755/269-28-dip_sml.jpg)
Z84C3006PEG
Manufacturer Part Number
Z84C3006PEG
Description
IC 6MHZ Z80 CMOS CTC 28-PDIP
Manufacturer
Zilog
Type
Counter/Timer Circuit (CTC)r
Series
Z80r
Specifications of Z84C3006PEG
Frequency
6MHz
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
8mA
Operating Temperature
-40°C ~ 100°C
Package / Case
28-DIP (0.600", 15.24mm)
Processor Series
Z84C3xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
6 MHz
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 100 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Filter Terminals
SMD
Ic Generic Number
84C30
Operating Temperature Min
-40°C
Operating Temperature Max
100°C
Clock Frequency
6MHz
Rohs Compliant
Yes
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
28
Supply Voltage Range
5V
Operating Temperature Range
-40°C To +100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Count
-
Lead Free Status / Rohs Status
Details
Other names
269-3910
Z84C3006PEG
Z84C3006PEG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z84C3006PEG
Manufacturer:
ZILOG
Quantity:
1 980
Company:
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Z84C3006PEG
Manufacturer:
Zilog
Quantity:
1 722
Company:
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Manufacturer:
ZILOG
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Company:
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Z84C3006PEG
Manufacturer:
WSI
Quantity:
4 970
Part Number:
Z84C3006PEG
Manufacturer:
ZILOG
Quantity:
20 000
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62
UM008005-0205
Z80 CPU
User’s Manual
Table 13. 16-Bit Arithmetic (Continued)
Rotate and Shift
A major feature of the Z80 is to rotate or shift data in the accumulator, any
general-purpose register, or any memory location. All the rotate and shift
Op Codes are depicted in Figure 14. Also included in the Z80 are
arithmetic and logical shift operations. These operations are useful in a
wide range of applications including integer multiplication and division.
Two BCD digit rotate instructions (
accumulator to be rotated with the two digits in a memory location
pointed to by register pair HL (See Figure 14). These instructions allow
for efficient BCD arithmetic.
Destination
ADD
ADD with carry and set flags ADC
SUB with carry and set flags SBC
Increment INC
Decrement DEC
RRD
HL
IX
IY
HL
HL
and
Z80 CPU Instruction Description
Source
09
DD
09
FD
09
ED
4A
ED
42
03
DB
RLD
) allow a digit in the
19
DD
19
FD
19
ED
5A
ED
52
13
1B
29
ED
6A
ED
62
23
2B
39
DD
39
FD
39
ED
7A
ED
72
33
3B
DD
29
DD
23
DD
2B
FD
29
FD
23
FD
2B
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