Z84C3006PEG Zilog, Z84C3006PEG Datasheet - Page 292

• Manufacturer Part Number: Z84C3006PEG
• Description: IC 6MHZ Z80 CMOS CTC 28-PDIP
• Manufacturer: Zilog
• Type: Counter/Timer Circuit (CTC)r
• Series: Z80r

Specifications of Z84C3006PEG

• Frequency: 6MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Processor Series: Z84C3xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 6 MHz
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Filter Terminals: SMD
• Ic Generic Number: 84C30
• Operating Temperature Min: -40°C
• Operating Temperature Max: 100°C
• Clock Frequency: 6MHz
• Rohs Compliant: Yes
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 28
• Supply Voltage Range: 5V
• Operating Temperature Range: -40°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Count: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3910; Z84C3006PEG

272
Operation:
Op Code:
Description: The contents of register C are placed on the bottom half (A0 through A7) of
Condition Bits Affected:
Example:
UM008005-0205
Z80 CPU
User’s Manual
(HL) ← (C), B ← B -1, HL ← HL + 1
INI
the address bus to select the I/O device at one of 256 possible ports.
Register B may be used as a byte counter, and its contents are placed on the
top half (A8 through A15) of the address bus at this time. Then one byte
from the selected port is placed on the data bus and written to the CPU. The
contents of the HL register pair are then placed on the address bus and the
input byte is written to the corresponding location of memory. Finally, the
byte counter is decremented and register pair HL is incremented.
S is unknown
Z is set if B–1 = 0, reset otherwise
H is unknown
P/V is unknown
N is set
C is not affected
If the contents of register C are
contents of the HL register pair are
peripheral device mapped to I /O port address
memory location
1001H
1
1
1
0
, and register B contains
M Cycles
1
1
4
0
0
1000H
1
0
contains
16 (4, 5, 3, 4)
1
0
INI
T States
07H
0
1
0FH
7BH
1000H
, the contents of register B are
.
1
0
, the HL register pair contains
ED
A2
, and byte
07H
4 MHz E.T.
. At execution of
4.00
7BH
Z80 Instruction Set
is available at the
10H
INI
, the