Z84C3006PEG Zilog, Z84C3006PEG Datasheet - Page 100
Z84C3006PEG
Manufacturer Part Number
Z84C3006PEG
Description
IC 6MHZ Z80 CMOS CTC 28-PDIP
Manufacturer
Zilog
Type
Counter/Timer Circuit (CTC)r
Series
Z80r
Specifications of Z84C3006PEG
Frequency
6MHz
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
8mA
Operating Temperature
-40°C ~ 100°C
Package / Case
28-DIP (0.600", 15.24mm)
Processor Series
Z84C3xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
6 MHz
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 100 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Filter Terminals
SMD
Ic Generic Number
84C30
Operating Temperature Min
-40°C
Operating Temperature Max
100°C
Clock Frequency
6MHz
Rohs Compliant
Yes
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
28
Supply Voltage Range
5V
Operating Temperature Range
-40°C To +100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Count
-
Lead Free Status / Rohs Status
Details
Other names
269-3910
Z84C3006PEG
Z84C3006PEG
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80
UM008005-0205
Z80 CPU
User’s Manual
Z80 Instruction Description
When inputting or outputting a byte between a memory location and an I/O
device (
Register is
from I/O devices using
Sign Flag
The Sign Flag (S) stores the state of the most-significant bit of the
Accumulator (bit 7). When the Z80 performs arithmetic operations on
signed numbers, the binary twos-complement notation is used to represent
and process numeric information. A positive number is identified by a
Bit 7. A negative number is identified by a 1. The binary equivalent of the
magnitude of a positive number is stored in bits 0 to 6 for a total range of
from
of the equivalent positive number. The total range for negative numbers is
from –
When inputting a byte from an I/O device to a register using an IN r, (C)
instruction, the S Flag indicates either positive (S = 0) or negative (S = 1)
data.
Execution time (E.T.) for each instruction is given in microseconds for an
assumed 4 MHz clock. Total machine cycles (M) are indicated with total
clock periods (T States). Also indicated are the number of T States for each
M cycle. For example:
M Cycles: 2T States: 7(4,3) 4 MHzE.T.: 1.75
indicates that the instruction consists of 2 machine cycles. The first cycle
contains 4 clock periods (T States). The second cycle contains 3 clock
periods for a total of 7 clock periods or T States. The instruction executes in
1.75 microseconds.
Register format is indicated for each instruction with the most-significant
bit to the left and the least-significant bit to the right.
0
1
to
INI
to –
127
0
,
, the Z flag is
128
IND
. A negative number is represented by the twos complement
.
,
OUTI
IN r
, and
1
, otherwise the Z flag is
, (
OUTD
C
), the Z flag is set to indicate a 0-byte input.
), if the result of decrementing the
0
. Also for byte inputs
Z80 Instruction Set
B
0
in
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