Z84C3006PEG Zilog, Z84C3006PEG Datasheet - Page 240

• Manufacturer Part Number: Z84C3006PEG
• Description: IC 6MHZ Z80 CMOS CTC 28-PDIP
• Manufacturer: Zilog
• Type: Counter/Timer Circuit (CTC)r
• Series: Z80r

Specifications of Z84C3006PEG

• Frequency: 6MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Processor Series: Z84C3xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 6 MHz
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Filter Terminals: SMD
• Ic Generic Number: 84C30
• Operating Temperature Min: -40°C
• Operating Temperature Max: 100°C
• Clock Frequency: 6MHz
• Rohs Compliant: Yes
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 28
• Supply Voltage Range: 5V
• Operating Temperature Range: -40°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Count: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3910; Z84C3006PEG

220
Operation:
Op Code:
Operands:
Description: The contents of the low order four bits (bits 3, 2, 1, and 0) of the memory
Condition Bits Affected:
UM008005-0205
Z80 CPU
User’s Manual
A
RLD
—
location (HL) are copied to the high order four bits (7, 6, 5, and 4) of that
same memory location; the previous contents of those high order four bits
are copied to the low order four bits of the Accumulator (register A); and
the previous contents of the low order four bits of the Accumulator are
copied to the low order four bits of memory location (HL). The contents of
the high order bits of the Accumulator are unaffected.
S is set if Accumulator is negative after operation; reset otherwise
Z is set if Accumulator is zero after operation; reset otherwise
H is reset
P/V is set if parity of Accumulator is even after operation; reset otherwise
N is reset
C is not affected
1
0
7
4
1
1
Note: (HL) means the memory location specified by the contents of the
HL register pair.
M Cycles
3
1
1
0
5
7
0
0
4
1
1
3
18 (4, 4, 3, 4, 3)
0
RLD
1
1
T States
0
1
1
1
ED
6F
4 MHz E.T.
4.50
Z80 Instruction Set