AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 9

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
List of Figures
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10. Segment Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 11. Floating-Point Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 12. FPU Status Word Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 13. FPU Control Word Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 14. FPU Tag Word Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 15. Packed Decimal Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 16. Precision Real Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 17. MMX™/3DNow!™ Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 18. MMX™ Technology Data Types . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 19. 3DNow!™ Technology Data Types . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 20. EFLAGS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 21. Control Register 4 (CR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 22. Control Register 3 (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 23. Control Register 2 (CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 24. Control Register 1 (CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 25. Control Register 0 (CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 26. Debug Register DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 27. Debug Register DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 28. Debug Registers DR5 and DR4. . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 29. Debug Registers DR3, DR2, DR1, and DR0. . . . . . . . . . . . . . . . 43
Figure 30. Machine-Check Address Register (MCAR) . . . . . . . . . . . . . . . . 45
Figure 31. Machine-Check Type Register (MCTR) . . . . . . . . . . . . . . . . . . . 45
Figure 32. Test Register 12 (TR12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 33. Time Stamp Counter (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 34. Extended Feature Enable Register (EFER) . . . . . . . . . . . . . . . 47
Figure 35. SYSCALL/SYSRET Target Address Register (STAR) . . . . . . . 48
Figure 36. Write Handling Control Register (WHCR) . . . . . . . . . . . . . . . . 48
AMD-K6™-IIIE+ Processor Block Diagram . . . . . . . . . . . . . . . . 13
Cache Sector Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
The Instruction Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AMD-K6™-IIIE+ Processor Decode Logic . . . . . . . . . . . . . . . . . 19
AMD-K6™-IIIE+ Processor Scheduler . . . . . . . . . . . . . . . . . . . . 22
Register X and Y Pipeline Functional Units . . . . . . . . . . . . . . . 24
EAX Register with 16-Bit and 8-Bit Name Components. . . . . . 28
Integer Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AMD-K6™-IIIE+ Embedded Processor Data Sheet
ix