AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 71

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
UC/WC Cacheability
Control Register
(UWCCR)
.
Figure 37. UC/WC Cacheability Control Register (UWCCR)
Processor State
Observability
Register (PSOR)
.
Figure 38. Processor State Observability Register (PSOR)
Chapter 3
Symbol
63
63
NOL2
STEP
BF
Physical Base Address 1
Symbol
UC1
WC1
No L2 Functionality
Processor Stepping
Bus Frequency Divisor
Reserved
Description
Uncacheable Memory Type
Write-Combining Memory Type
Description
49
MTRR1
The AMD-K6-IIIE+ processor provides two variable-range
Memory Type Range Registers (MTRRs)—MTRR0 and
MTRR1—that each specify a range of memory. Each range can
be defined as uncacheable (UC) or write-combining (WC)
memory. For more information, see “Memory Type Range
Re gist ers” o n pag e 231 . The UWCCR reg ist er is M SR
C000_0085h.
The AMD-K6-IIIE+ processor provides the Processor State
Observability Register (PSOR). The PSOR is defined as shown
i n Fi g u re 3 8 fo r a l l s t a n d a rd - p ow e r ve rs i o n s o f t h e
AMD-K6-IIIE+ processor. For a description of the PSOR register
supported by the low-power versions of the processor, see
page 148.
The PSOR register is MSR C000_0087h.
Physical Address Mask 1
48
2-0
Bit
8
7-4
Bits
32
33
Software Environment
34
W
33
C
1
32
U
C
1
31
Physical Base Address 0
Symbol
UC0
WC0
AMD-K6™-IIIE+ Embedded Processor Data Sheet
Description
Uncacheable Memory Type
Write-Combining Memory Type
9
MTRR0
17
N
O
8
L
2
16
Physical Address Mask 0
7
STEP
4
Bits
0
1
3
2
2
W
C
0
1
BF
0
U
C
0
0
49