AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 289

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
Figure 94. L2 Data - EAX
L2 Tag Reads
Chapter 13
31
as illustrated in Figure 94. Similarly, if the L2 cache data is
written, the write data is taken from EAX.
If the L2 tag is read (as opposed to reading the cache data), the
result is placed in EAX in the format as illustrated in Figure 95
on page 268. Similarly, if the L2 tag is written, the write data is
taken from EAX. When accessing the L2 tag, the Line, Octet,
and Dword fields of the EDX register are ignored.
When writing to the L2 tag, special consideration must be given
to the least significant bit of the Tag field of the EAX register—
EAX[15]. The length of the L2 tag required to support the
256-Kbyte L2 cache on the AMD-K6-IIIE+ processor is 16 bits,
which corresponds to bits 31:16 of the EAX register. However,
the processor provides a total of 17 bits for storing the L2 tag—
that is, 16 bits for the tag (EAX[31:16]), plus an additional bit
for internal purposes (EAX[15]). During normal operation, the
processor ensures that this additional bit (bit 15) always
corresponds to the set in which the tag resides. Note that bits
15:6 of the address determine the set, in which case if bit 15 is
equal to 0, it addresses sets 0 through 511, and if bit 15 is equal
to 1, it addresses sets 512 through 1023.
In order to set the full 17-bit L2 tag properly when using the
L2AAR register, EAX[15] must likewise correspond to the set in
which the tag is being written—that is, EAX[15] must be equal
to EDX[15] (refer to Figure 93 on page 266 and Figure 95 on
page 268).
It is important to note that this special consideration is required
if the processor will subsequently be expected to properly
execute instructions or access data from the L2 cache following
the setup of the L2 cache by means of the L2AAR register. If the
intent of using the L2AAR register is solely to test or debug the
L2 cache without the subsequent in te nt of ex ecuting
instructions or accessing data from the L2 cache, then this
consideration is not required.
Test and Debug
Data
AMD-K6™-IIIE+ Embedded Processor Data Sheet
0
267