AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 286

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
13.5
Level-2 Cache Array
Access Register
(L2AAR)
264
L2 Cache and Tag Array Testing
initiated by the system logic, including the execution of
writeback cycles when a modified cache line is hit.
While the L1 and L2 are inhibited, the processor continues to
drive the PCD output signal appropriately, which system logic
can use to control external L3 caching.
In order to completely disable the L1 and L2 caches so that no
valid lines exist in the cache, the Cache Inhibit bit must be set
to 1 and the cache must be flushed in one of the following ways:
The AMD-K6-IIIE+ processor provides the Level-2 Cache Array
Access Register (L2AAR) that allows for direct access to the L2
cache and L2 tag arrays. The 256-Kbyte L2 cache in the
AMD-K6-IIIE+ is organized as shown in Figure 91 on page 265:
Each line within a sector contains its own MESI state bits, and
associated with each sector is a tag and LRU (least recently
used) information.
Asserting the FLUSH# input signal
Executing the WBINVD instruction
Executing the INVD instruction (modified cache lines are
not written back to memory)
Using the Page Flush/Invalidate Register (PFIR) (see “Page
Flush/Invalidate Register (PFIR)” on page 223)
Four 64-Kbyte ways
Each way contains 1024 sets
Each set contains four 64-byte sectors (one sector in each
way)
Each sector contains two 32-byte cache lines
Each cache line contains four 8-byte octets
Each octet contains an upper and lower dword (4 bytes)
Preliminary Information
Test and Debug
23543A/0—September 2000
Chapter 13