AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 154

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
5.45
Pin Attribute
Summary
Sampled
132
STPCLK# (Stop Clock)
Input, Internal Pullup
The assertion of STPCLK# causes the processor to enter the
Stop Grant state, during which the processor’s internal clock is
stopped. From the Stop Grant state, the processor can
subsequently transition to the Stop Clock state, in which the
bus clock CLK is stopped. Upon recognizing STPCLK#, the
processor performs the following actions, in the order shown:
1. Flushes its instruction pipelines
2. Completes all pending and in-progress bus cycles
3. Acknowledges the STPCLK# assertion by executing a Stop
4. Stops its internal clock after BRDY# of the Stop Grant
5. Enters the Stop Clock state if the system logic stops the bus
See “Clock Control” on page 277 for more details regarding
clock control.
STPCLK# is sampled as a level-sensitive input on every clock
edge but is not recognized until the next instruction boundary.
System logic can drive the signal either synchronously or
asynchronously. If it is asserted asynchronously, it must be
asserted for a minimum pulse width of two clocks.
STPCLK# must remain asserted until recognized, which is
indicated by the completion of the Stop Grant special cycle.
Grant special bus cycle (see Table 24 on page 142)
special bus cycle is sampled asserted and after EWBE# is
sampled asserted (if EWBE# is masked off, then entry into
the Stop Grant state is not affected by EWBE#)
clock CLK (optional)
Preliminary Information
Signal Descriptions
23543A/0—September 2000
Chapter 5