AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 142

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
5.33
Pin Attribute
Summary
Driven and Floated
120
LOCK# (Bus Lock)
Output
The processor asserts LOCK# during a sequence of bus cycles to
ensure that the cycles are completed without allowing other bus
masters to intervene. Locked operations consist of two to five
bus cycles. LOCK# is asserted during the following operations:
In order to ensure that locked operations appear on the bus and
are visible to the entire system, any data operands addressed
during a locked cycle that reside in the processor’s caches are
flushed and invalidated from the caches prior to the locked
operation. If the cache line is in the modified state, it is written
back and invalidated prior to the locked operation. Likewise,
any data read during a locked operation is not cached.
The processor is designed so that LOCK# does not glitch.
During a locked cycle, LOCK# is asserted off the same clock
edge on which ADS# is asserted and remains asserted until the
last BRDY# of the last bus cycle is sampled asserted. The
processor negates LOCK# for at least one clock between
consecutive sequences of locked operations to allow the system
logic to arbitrate for the bus.
LOCK# is floated off the clock edge on which BOFF# is sampled
asserted and off the clock edge that the processor asserts HLDA
in response to HOLD. When LOCK# is floated due to BOFF#
sampled asserted, the system logic is responsible for preserving
the lock condition while LOCK# is in the high-impedance state.
An interrupt acknowledge sequence
Descriptor Table accesses
Page Directory and Page Table accesses
XCHG instruction
An instruction with an allowable LOCK prefix
Preliminary Information
Signal Descriptions
23543A/0—September 2000
Chapter 5