AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 169

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
Figure 56. Bus Divisor and Voltage ID Control (BVC) Field
Table 27. Bus Divisor and Voltage ID Control (BVC) Definition
Notes:
1. All bits default to 0 when RESET is asserted, except the VIDO bits which default to 01010b.
Chapter 6
31-12
Bit
9-8
4-0
7-5
11
10
Symbol
31
SGTC
BVCM
VIDC
BDC
IBF[2:0]
VIDO
Description
Stop Grant Time-Out Counter (SGTC)
Bus Divisor and VID Change Mode
(BVCM)
Voltage ID Control (VIDC)
Bus Divisor Control (BDC)
Internal BF Divisor (IBF[2:0])
Voltage ID Output (VIDO)
Description
Stop Grant Time-out Counter
Bus Divisor and VID Change Mode
Voltage ID Control
Bus Divisor Control
Internal BF Divisor
Voltage ID Output
Reserved
AMD PowerNow!™ Technology
SGTC
R/W Function
R/W
R/W
R/W
R/W
R/W
W
Bits
31-12
11
10
9-8
7-5
4-0
Writing a non-zero value to this field causes the processor to enter the
EPM Stop Grant state internally. This 20-bit value is multiplied by 4096
to determine the duration of the EPM Stop Grant state, measured in
processor bus clocks.
This bit controls the mode in which the bus-divisor and the voltage
control bits are allowed to change. If BVCM=0, the Bus Divisor and
Voltage ID changes take effect only upon entering the EPM Stop Grant
state as a result of the SGTC field being programmed. BVCM=1 is
reserved.
This bit controls the mode of Voltage ID control. If VIDC=0, the proces-
sor VID[4:0] pins are unchanged upon entering the EPM Stop Grant
state. If VIDC=1, the processor VID[4:0] pins are programmed to the
VIDO value upon entering the EPM Stop Grant state. BIOS should ini-
tialize this bit to 1 during the POST routine.
This 2-bit field controls the mode of Bus Divisor control. If
BDC[1:0]=00b, the BF[2:0] pins are sampled at the falling edge of
RESET. If BDC[1:0]=1xb, the IBF[2:0] field is sampled upon entering the
EPM Stop Grant state. BDC[1:0]=01b is reserved. BIOS should initialize
these bits to 10b during the POST routine.
If BDC[1:0]=1xb, the processor EBF[2:0] field of the PSOR is pro-
grammed to the IBF[2:0] value upon entering the EPM Stop Grant
state.
This 5-bit value is driven out on the processor VID[4:0] pins upon
entering the EPM Stop Grant state if the VIDC bit=1. These bits are ini-
tialized to 01010b and driven on the processor VID[4:0] pins at RESET.
1
AMD-K6™-IIIE+ Embedded Processor Data Sheet
12
11 10
M
B
V
C
V
D
C
I
9 8 7
BDC
IBF[2:0]
5
4
VIDO
0
147