AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 121

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AMD-K6-IIIE+550ACR

Manufacturer Part Number
AMD-K6-IIIE+550ACR
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of AMD-K6-IIIE+550ACR

Lead Free Status / RoHS Status
Not Compliant
23543A/0—September 2000
5.8
Pin Attribute
Summary
Driven
Chapter 5
APCHK# (Address Parity Check)
Output
If the processor detects an address parity error during an
inquire cycle, APCHK# is asserted for one clock. The processor
does not take an internal exception as the result of detecting an
address bus parity check, and system logic must respond
appropriately to the assertion of this signal.
The processor is designed so that APCHK # does not glitch,
enabling the signal to be used as a clocking source for system
logic.
APCHK# is driven valid off the clock edge after the clock edge
on which the processor samples EADS# asserted. It is negated
off the next clock edge.
APCHK# is always driven except in the Three-State Test mode.
Signal Descriptions
AMD-K6™-IIIE+ Embedded Processor Data Sheet
99

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