AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 86

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
Opcode Bytes
ModR/M Byte
Decode Type
RISC86® Operation
64
The second and third columns list all applicable opcode bytes.
The fourth column lists the modR/M byte when used by the
instruction. The modR/M byte defines the instruction as a
re g i st e r o r m e m o ry fo r m . I f m o d R / M b i t s 7 a n d 6 a re
documented as mm (memory form), mm can only be 10b, 01b or
00b.
The fifth column lists the type of instruction decode — short,
long, and vector. The AMD-K6-IIIE+ processor decode logic can
process two short, one long, or one vector decode per clock.
The sixth column lists the type of RISC86 operation(s) required
for the instruction. The operation types and corresponding
execution units are as follows:
mmreg1—MMX/3DNow! register defined by bits 5, 4, and 3
of the modR/M byte
mmreg2—MMX/3DNow! register defined by bits 2, 1, and 0
of the modR/M byte
mreg16/32—word or doubleword integer register, or word or
doubleword integer value in memory defined by the
modR/M byte
mreg8—byte integer register or byte integer value in
memory defined by the modR/M byte
reg8—byte integer register defined by instruction byte(s) or
bits 5, 4, and 3 of the modR/M byte
reg16/32—word or doubleword integer register defined by
instruction byte(s) or bits 5, 4, and 3 of the modR/M byte
alu—either of the integer execution units
alux—integer X execution unit only
branch—branch condition unit
float—floating-point execution unit
limm—load immediate, instruction control unit
load, fload, mload—load unit
meu—multimedia execution units for MMX and 3DNow!
instructions
store, fstore, mstore—store unit
Preliminary Information
Software Environment
23543A/0—September 2000
Chapter 3