AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 44
AMD-K6-IIIE+550ACR
Manufacturer Part Number
AMD-K6-IIIE+550ACR
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.AMD-K6-IIIE550ACR.pdf
(370 pages)
Specifications of AMD-K6-IIIE+550ACR
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AMD-K6™-IIIE+ Embedded Processor Data Sheet
Figure 5. AMD-K6™-IIIE+ Processor Scheduler
2.5
22
Centralized RISC86
Operation Scheduler
Execution Units
®
The AMD-K6-IIIE+ processor contains ten parallel execution
units—store, load, integer X ALU, integer Y ALU, MMX ALU
(X), MMX ALU (Y), MMX/3DNow! multiplier, 3DNow! ALU,
floating-point, and branch condition. Each unit is independent
and capable of handling the RISC86 operations issued to it.
Table 1 on page 23 details the execution units, functions
performed within these units, operation latency, and operation
throughput.
Note that the integer, MMX, and 3DNow! execution units share
the register X and Y issue pipelines. See “Register X and Y
Pipelines” on page 24.
The store and load execution units are two-stage pipelined
designs.
RISC86 #0
The store unit performs data writes and register calculation
for LEA/PUSH instructions. Data memory and register
Preliminary Information
RISC86 #1
Internal Architecture
RISC86 Operation Buffer
From Decode Logic
RISC86 #2
RISC86 #3
RISC86 Issue Buses
23543A/0—September 2000
Chapter 2
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