AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 330

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

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AMD-K6™-IIIE+ Embedded Processor Data Sheet
16.9
Table 68. RESET and Configuration Signals for 100-MHz Bus Operation
Notes:
1. BF[2:0] must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of RESET.
2. To be sampled on a specific clock edge, setup and hold times must be met the clock edge before the clock edge on which RESET is
3. If asserted asynchronously, these signals must meet a minimum setup and hold time of two clocks relative to the negation of RESET.
308
Symbol Parameter Description
t
t
t
t
t
sampled negated.
t
100
102
t
t
t
t
t
101
t
t
94
95
99
90
91
92
93
96
97
98
1
1
2
3
2
3
RESET Setup Time
RESET Hold Time
RESET Pulse Width, V
RESET Active After V
BF[2:0] Setup Time
BF[2:0] Hold Time
Intentionally left blank
Intentionally left blank
Intentionally left blank
FLUSH# Setup Time
FLUSH# Hold Time
FLUSH# Setup Time
FLUSH# Hold Time
RESET and Test Signal Timing
CC
CC
and CLK Stable
and CLK Stable
Signal Switching Characteristics
Preliminary Information
15 clocks
2 clocks
2 clocks
2 clocks
1.0 ms
1.0 ms
1.7 ns
1.0 ns
1.7 ns
1.0 ns
Min
Preliminary Data
Max
23543A/0—September 2000
Chapter 16
Figure
109
109
109
109
109
109
109
109
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