LPC47M107S-MS Standard Microsystems (SMSC), LPC47M107S-MS Datasheet - Page 94

• Manufacturer Part Number: LPC47M107S-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M107S-MS

• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

Reset and Initialization
The SER_IRQ bus uses nPCI_RESET as its reset signal. The SER_IRQ pin is tri-stated by all agents while
nPCI_RESET is active. With reset, SER_IRQ Slaves are put into the (continuous) IDLE mode. The Host Controller is
responsible for starting the initial SER_IRQ Cycle to collect system’s IRQ/Data default values. The system then
follows with the Continuous/Quiet mode protocol (Stop Frame pulse width) for subsequent SER_IRQ Cycles. It is
Host Controller’s responsibility to provide the default values to 8259’s and other system logic before the first
SER_IRQ Cycle is performed. For SER_IRQ system suspend, insertion, or removal application, the Host controller
should be programmed into Continuous (IDLE) mode first. This is to guarantee SER_IRQ bus is in IDLE state before
the system configuration changes.
The LPC47M10x is a Super I/O and Universal Keyboard Controller that is designed for intelligent keyboard management
in desktop computer applications.
The Universal Keyboard Controller uses an 8042 microcontroller CPU core.
LPC47M10x enhancements to the 8042. For general information about the 8042, refer to the "Hardware Description of
the 8042" in the 8-Bit Embedded Controller Handbook.
KIRQ is the Keyboard IRQ
MIRQ is the Mouse IRQ
Port 21 is used to create a GATEA20 signal from the LPC47M10x.
8042A
TST0
TST1
P27
P10
P26
P23
P22
P11
8042 KEYBOARD CONTROLLER DESCRIPTION
Keyboard and Mouse Interface
Page 94
LS05
This section concentrates on the
KDAT
KCLK
MCLK
MDAT