LPC47M107S-MS Standard Microsystems (SMSC), LPC47M107S-MS Datasheet - Page 13

• Manufacturer Part Number: LPC47M107S-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M107S-MS

• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

3 VOLT OPERATION / 5 VOLT TOLERANCE
The LPC47M10x is a 3.3 Volt part. It is intended solely for 3.3V applications. Non-LPC bus pins are 5V tolerant; that
is, the input voltage is 5.5V max, and the I/O buffer output pads are backdrive protected.
The LPC interface pins are 3.3 Volt only. These signals meet PCI DC specifications for 3.3V signaling. These pins
are:
•
•
•
•
The input voltage for all other pins is 5.5V max. These pins include all non-LPC Bus pins and the following pins:
•
•
•
•
POWER FUNCTIONALITY
The LPC47M10x has three power planes: VCC, VTR and VREF.
VCC Power
The LPC47M10x is a 3.3 Volt part. The VCC supply is 3.3 Volts (nominal). See the Operational Description Section
and the Maximum Current Values sub-section.
VTR Support
The LPC47M10x requires a trickle supply (V
PME interface when V
Section. The maximum VTR current that is required depends on the functions that are used in the part. See Trickle
Power Functionality and Maximum Current Values sub-sections. If the LPC47M10x is not intended to provide wake-
up capabilities on standby current, V
registers and the PME interface. The V
Note: If V
potential at least 10 μs before V
difference between the two supplies must not exceed 500mV.
Internal PWRGOOD
An internal PWRGOOD logical control is included to minimize the effects of pin-state uncertainty in the host interface
as V
LPC47M10x host interface is active. When the internal PWRGOOD signal is “0” (inactive), V
the LPC47M10x host interface is inactive; that is, LPC bus reads and writes will not be decoded.
The LPC47M10x device pins nIO_PME, CLOCKI32, KDAT, MDAT, IRRX, nRI1, nRI2, RXD2 and most GPIOs (as
input) are part of the PME interface and remain active when the internal PWRGOOD signal has gone inactive,
provided V
active when the internal PWRGOOD signal has gone inactive, provided V
Functionality section. The internal PWRGOOD signal is also used to disable the IR Half Duplex Timeout.
32.768 kHz Trickle Clock Input
The LPC47M10x utilizes a 32.768 kHz trickle input to supply a clock signal for the fan tachometer logic, LED blink
and wake on specific key function. See the following section for more information.
LAD[3:0]
nLFRAME
nLDRQ
nLPCPD
nPCI_RESET
PCI_CLK
SER_IRQ
nIO_PME
cc
cycles on and off. When the internal PWRGOOD signal is “1” (active), V
TR
TR
is to be used for programmable wake-up events when V
is powered. The IRTX2/GP35, GP53/TXD2(IRTX), GP60/LED1 and GP61/LED2 pins also remain
CC
is removed. The VTR supply is 3.3 Volts (nominal). See the Operational Description
cc
TR
begins a power-on cycle. When V
can be connected to V
TR
pin generates a V
TR
) to provide sleep current for the programmable wake-up events in the
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TR
CC
Power-on-Reset signal to initialize these components.
. V
TR
CC
powers the IR interface, the PME configuration
is removed, V
TR
and V
TR
cc
is powered. See Trickle Power
are fully powered, the potential
TR
cc
must be at its full minimum
> 2.3V (nominal), and the
cc
≤ 2.3V (nominal), and