LPC47M107S-MS Standard Microsystems (SMSC), LPC47M107S-MS Datasheet - Page 152

• Manufacturer Part Number: LPC47M107S-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M107S-MS

• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

Note 1: This chip uses address bits [A11:A0] to decode the base address of each of its logical devices. Bit 6 of the
Note 2: The Configuration Port is at either 0x02E or 0x04E (for SYSOPT=0 or SYSOPT=1) at power up and can be
Note:
Primary Interrupt
Select
Default=0x00 or
0x06
on VCC POR,
VTR POR,
HARD RESET
and
SOFT RESET
NAME
(Note 1)
LOGICAL
NUMBER
OSC Global Configuration Register (CR24) must be set to ‘1’ and Address Bits [A15:A12] must be ‘0’ for 16 bit
address qualification.
replaced via the global configuration registers at 0x26 and 0x27.
An Interrupt is activated by setting the Interrupt Request Level Select 0 register to a non-zero value AND :
And by setting the OUT2 bit in the UART's Modem Control (MCR) Register.
DEVICE
Config.
0x0A
0x0B
Port
For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register.
For the PP logical device by setting IRQE, bit D4 of the Control Port and in addition
For the PP logical device in ECP mode by clearing serviceIntr, bit D2 of the ecr.
For the Serial Port logical device by setting any combination of bits D0-D3 in the IER
0x70 (R/W)
REG INDEX
Config. Port
LOGICAL
Registers
MPU-401
DEVICE
Runtime
Table 65 - I/O Base Address Configuration Register Description
Table 66 - Interrupt Select Configuration Register Description
Bits[3:0] selects which interrupt is used for the primary
Interrupt.
Note: All interrupts are edge high (except ECP/EPP)
Note: nSMI is active low
REGISTER
0x26, 0x27
0x60,0x61
0x60,0x61
(Note 2)
INDEX
0x00= no interrupt selected
0x01= IRQ1
0x02= IRQ2/nSMI
0x03= IRQ3
0x04= IRQ4
0x05= IRQ5
0x06= IRQ6
0x07= IRQ7
0x08= IRQ8
0x09= IRQ9
0x0A= IRQ10
0x0B= IRQ11
0x0C= IRQ12
0x0D= IRQ13
0x0E= IRQ14
0x0F= IRQ15
Page 152
on 128-byte boundaries
On 2 byte boundaries
on 2-byte boundaries
DEFINITION
[0x0100:0x0FFE]
[0x0000:0x0F7F]
0x0100:0x0FFE
BASE I/O
(NOTE 1)
RANGE
+00 : PME Status
.
.
.
+5F : Keyboard Scan
Code
(See Table in “Runtime
Registers” section for Full
List)
+0: Data
+1: Status/Command
See Configuration
Registers in Table 54.
Accessed through the
index and DATA ports
located at the
Configuration Port
address and the
Configuration Port
address +1 respectively.
BASE OFFSETS
FIXED
STATE
C