LPC47M107S-MS Standard Microsystems (SMSC), LPC47M107S-MS Datasheet - Page 172

• Manufacturer Part Number: LPC47M107S-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M107S-MS

• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

Output Drivers
To facilitate higher performance data transfer, the use of balanced CMOS active drivers for critical signals (Data,
HostAck, HostClk, PeriphAck, PeriphClk) are used in ECP Mode. Because the use of active drivers can present
compatibility problems in Compatible Mode (the control signals, by tradition, are specified as open-collector), the
drivers are dynamically changed from open-collector to totem-pole. The timing for the dynamic driver change is
specified in then IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July 14,
1993, available from Microsoft. The dynamic driver change must be implemented properly to prevent glitching the
outputs.
Note 1: The data is held until BUSY goes inactive or for time t3, whichever is longer. This only applies if another data
NAME
nSTROBE
t1
t2
t3
t4
t5
t6
PD<7:0>
BUSY
transfer is pending. If no other data transfer is pending, the data is held indefinitely.
PDATA Valid to nSTROBE Active
nSTROBE Active Pulse Width
PDATA Hold from nSTROBE Inactive (Note 1)
nSTROBE Active to BUSY Active
BUSY Inactive to nSTROBE Active
BUSY Inactive to PDATA Invalid (Note 1)
DESCRIPTION
FIGURE 22 - PARALLEL PORT FIFO TIMING
t1
Page 172
t4
t2
MIN
600
600
450
680
80
t3
TYP
t6
t5
MAX
500
UNITS
ns
ns
ns
ns
ns
ns