LPC47M107S-MS Standard Microsystems (SMSC), LPC47M107S-MS Datasheet - Page 27

• Manufacturer Part Number: LPC47M107S-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M107S-MS

• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

BIT 2 through 4 PRECOMPENSATION SELECT
These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 7
shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track
number to start precompensation. this starting track number can be changed by the configure command.
BIT 5 UNDEFINED
Should be written as a logic "0".
BIT 6 LOW POWER
A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy controller clock and
data separator circuits will be turned off. The controller will come out of manual low power mode after a software reset
or access to the Data Register or Main Status Register.
BIT 7 SOFTWARE RESET
This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing.
Note: The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, located at the offset 0x1F in the runtime
register block. Separator circuits will be turned off.
Drive Rate Table (Recommended)
Note 1: The DRATE and DENSEL values are mapped onto the DRVDEN pins.
DRT1
DRIVE RATE
0
0
0
0
0
0
0
0
1
1
1
1
PRECOMP
432
111
001
010
011
100
101
110
000
DRT0
0
0
0
0
1
1
1
1
0
0
0
0
SEL1
Table 7 - Precompensation Delays
00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format
01 = 3-Mode Drive
10 = 2 Meg Tape
DATA RATE
1
0
0
1
1
0
0
1
1
0
0
1
Default: See Table 10
SEL0
PRECOMPENSATION DELAY (nsec)
1
0
1
0
1
0
1
0
1
0
1
0
<2Mbps
Table 8 - Data Rates
125.00
166.67
208.33
250.00
Default
41.67
83.34
0.00
1Meg
1Meg
1Meg
2Meg
MFM
500
300
250
500
500
250
500
250
Page 27
DATA RATE
The controller will come out of manual low power.
250
150
125
250
250
125
250
125
FM
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DENSEL
2Mbps
Default
104.2
20.8
41.7
62.5
83.3
125
0
1
1
0
0
1
1
0
0
1
1
0
0
DRATE(1)
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0